Commit 6bc2b6c6 authored by Bo-Cun Chen's avatar Bo-Cun Chen Committed by Jakub Kicinski
Browse files

net: ethernet: mtk_eth_soc: reapply mdc divider on reset 



In the current method, the MDC divider was reset to the default setting
of 2.5MHz after the NETSYS SER. Therefore, we need to reapply the MDC
divider configuration function in mtk_hw_init() after reset.

Fixes: c0a44003 ("net: ethernet: mtk_eth_soc: set MDIO bus clock frequency")
Signed-off-by: default avatarBo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Link: https://patch.msgid.link/8ab7381447e6cdcb317d5b5a6ddd90a1734efcb0.1744764277.git.daniel@makrotopia.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8e57ce3c

drivers/net/ethernet/mediatek/mtk_eth_soc.c

+24 −15
Original line number Diff line number Diff line
@@ -871,9 +871,25 @@ static const struct phylink_mac_ops mtk_phylink_ops = { 
	.mac_enable_tx_lpi = mtk_mac_enable_tx_lpi,

};



static void mtk_mdio_config(struct mtk_eth *eth)

{

	u32 val;



	/* Configure MDC Divider */

	val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider);



	/* Configure MDC Turbo Mode */

	if (mtk_is_netsys_v3_or_greater(eth))

		mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);

	else

		val |= PPSC_MDC_TURBO;



	mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);

}



static int mtk_mdio_init(struct mtk_eth *eth)

{

	unsigned int max_clk = 2500000, divider;

	unsigned int max_clk = 2500000;

	struct device_node *mii_np;

	int ret;

	u32 val;
@@ -908,20 +924,9 @@ static int mtk_mdio_init(struct mtk_eth *eth) 
		}

		max_clk = val;

	}

	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);



	/* Configure MDC Turbo Mode */

	if (mtk_is_netsys_v3_or_greater(eth))

		mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);



	/* Configure MDC Divider */

	val = FIELD_PREP(PPSC_MDC_CFG, divider);

	if (!mtk_is_netsys_v3_or_greater(eth))

		val |= PPSC_MDC_TURBO;

	mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);



	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);



	eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);

	mtk_mdio_config(eth);

	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider);

	ret = of_mdiobus_register(eth->mii_bus, mii_np);



err_put_node:
@@ -3974,6 +3979,10 @@ static int mtk_hw_init(struct mtk_eth *eth, bool reset) 
	else

		mtk_hw_reset(eth);



	/* No MT7628/88 support yet */

	if (reset && !MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))

		mtk_mdio_config(eth);



	if (mtk_is_netsys_v3_or_greater(eth)) {

		/* Set FE to PDMAv2 if necessary */

		val = mtk_r32(eth, MTK_FE_GLO_MISC);

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+1 −0
Original line number Diff line number Diff line
@@ -1271,6 +1271,7 @@ struct mtk_eth { 
	struct clk			*clks[MTK_CLK_MAX];



	struct mii_bus			*mii_bus;

	unsigned int			mdc_divider;

	struct work_struct		pending_work;

	unsigned long			state;