Merge tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (6bfd2d44) · Commits · git / linux-net

Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)

		maintainers:
		- Anup Patel <anup@brainfault.org>

		description:
		The RISC-V advanced interrupt architecture (AIA) defines an advanced
		platform level interrupt controller (APLIC) for handling wired interrupts
		in a RISC-V platform. The RISC-V AIA specification can be found at
		https://github.com/riscv/riscv-aia.

		The RISC-V APLIC is implemented as hierarchical APLIC domains where all
		interrupt sources connect to the root APLIC domain and a parent APLIC
		domain can delegate interrupt sources to it's child APLIC domains. There
		is one device tree node for each APLIC domain.

		allOf:
		- $ref: /schemas/interrupt-controller.yaml#

		properties:
		compatible:
		items:
		- enum:
		- qemu,aplic
		- const: riscv,aplic

		reg:
		maxItems: 1

		interrupt-controller: true

		"#interrupt-cells":
		const: 2

		interrupts-extended:
		minItems: 1
		maxItems: 16384
		description:
		Given APLIC domain directly injects external interrupts to a set of
		RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
		node, which has a CPU node (i.e. RISC-V HART) as parent.

		msi-parent:
		description:
		Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
		message signaled interrupt controller (IMSIC). If both "msi-parent" and
		"interrupts-extended" properties are present then it means the APLIC
		domain supports both MSI mode and Direct mode in HW. In this case, the
		APLIC driver has to choose between MSI mode or Direct mode.

		riscv,num-sources:
		$ref: /schemas/types.yaml#/definitions/uint32
		minimum: 1
		maximum: 1023
		description:
		Specifies the number of wired interrupt sources supported by this
		APLIC domain.

		riscv,children:
		$ref: /schemas/types.yaml#/definitions/phandle-array
		minItems: 1
		maxItems: 1024
		items:
		maxItems: 1
		description:
		A list of child APLIC domains for the given APLIC domain. Each child
		APLIC domain is assigned a child index in increasing order, with the
		first child APLIC domain assigned child index 0. The APLIC domain child
		index is used by firmware to delegate interrupts from the given APLIC
		domain to a particular child APLIC domain.

		riscv,delegation:
		$ref: /schemas/types.yaml#/definitions/phandle-array
		minItems: 1
		maxItems: 1024
		items:
		items:
		- description: child APLIC domain phandle
		- description: first interrupt number of the parent APLIC domain (inclusive)
		- description: last interrupt number of the parent APLIC domain (inclusive)
		description:
		A interrupt delegation list where each entry is a triple consisting
		of child APLIC domain phandle, first interrupt number of the parent
		APLIC domain, and last interrupt number of the parent APLIC domain.
		Firmware must configure interrupt delegation registers based on
		interrupt delegation list.

		dependencies:
		riscv,delegation: [ "riscv,children" ]

		required:
		- compatible
		- reg
		- interrupt-controller
		- "#interrupt-cells"
		- riscv,num-sources

		anyOf:
		- required:
		- interrupts-extended
		- required:
		- msi-parent

		unevaluatedProperties: false

		examples:
		- \|
		// Example 1 (APLIC domains directly injecting interrupt to HARTs):

		interrupt-controller@c000000 {
		compatible = "qemu,aplic", "riscv,aplic";
		interrupts-extended = <&cpu1_intc 11>,
		<&cpu2_intc 11>,
		<&cpu3_intc 11>,
		<&cpu4_intc 11>;
		reg = <0xc000000 0x4080>;
		interrupt-controller;
		#interrupt-cells = <2>;
		riscv,num-sources = <63>;
		riscv,children = <&aplic1>, <&aplic2>;
		riscv,delegation = <&aplic1 1 63>;
		};

		aplic1: interrupt-controller@d000000 {
		compatible = "qemu,aplic", "riscv,aplic";
		interrupts-extended = <&cpu1_intc 9>,
		<&cpu2_intc 9>;
		reg = <0xd000000 0x4080>;
		interrupt-controller;
		#interrupt-cells = <2>;
		riscv,num-sources = <63>;
		};

		aplic2: interrupt-controller@e000000 {
		compatible = "qemu,aplic", "riscv,aplic";
		interrupts-extended = <&cpu3_intc 9>,
		<&cpu4_intc 9>;
		reg = <0xe000000 0x4080>;
		interrupt-controller;
		#interrupt-cells = <2>;
		riscv,num-sources = <63>;
		};

		- \|
		// Example 2 (APLIC domains forwarding interrupts as MSIs):

		interrupt-controller@c000000 {
		compatible = "qemu,aplic", "riscv,aplic";
		msi-parent = <&imsic_mlevel>;
		reg = <0xc000000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;
		riscv,num-sources = <63>;
		riscv,children = <&aplic3>;
		riscv,delegation = <&aplic3 1 63>;
		};

		aplic3: interrupt-controller@d000000 {
		compatible = "qemu,aplic", "riscv,aplic";
		msi-parent = <&imsic_slevel>;
		reg = <0xd000000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;
		riscv,num-sources = <63>;
		};
		...

Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: RISC-V Incoming MSI Controller (IMSIC)

		maintainers:
		- Anup Patel <anup@brainfault.org>

		description: \|
		The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
		MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
		AIA specification can be found at https://github.com/riscv/riscv-aia.

		The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
		for each privilege level (machine or supervisor). The configuration of
		a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
		space to receive MSIs from devices. Each IMSIC interrupt file supports a
		fixed number of interrupt identities (to distinguish MSIs from devices)
		which is same for given privilege level across CPUs (or HARTs).

		The device tree of a RISC-V platform will have one IMSIC device tree node
		for each privilege level (machine or supervisor) which collectively describe
		IMSIC interrupt files at that privilege level across CPUs (or HARTs).

		The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
		follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
		group is a set of IMSIC interrupt files co-located in MMIO space and we can
		have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
		RISC-V platform. The MSI target address of a IMSIC interrupt file at given
		privilege level (machine or supervisor) encodes group index, HART index,
		and guest index (shown below).

		XLEN-1 > (HART Index MSB) 12 0
		\| \| \| \|
		-------------------------------------------------------------
		\|xxxxxx\|Group Index\|xxxxxxxxxxx\|HART Index\|Guest Index\| 0 \|
		-------------------------------------------------------------

		allOf:
		- $ref: /schemas/interrupt-controller.yaml#
		- $ref: /schemas/interrupt-controller/msi-controller.yaml#

		properties:
		compatible:
		items:
		- enum:
		- qemu,imsics
		- const: riscv,imsics

		reg:
		minItems: 1
		maxItems: 16384
		description:
		Base address of each IMSIC group.

		interrupt-controller: true

		"#interrupt-cells":
		const: 0

		msi-controller: true

		"#msi-cells":
		const: 0

		interrupts-extended:
		minItems: 1
		maxItems: 16384
		description:
		This property represents the set of CPUs (or HARTs) for which given
		device tree node describes the IMSIC interrupt files. Each node pointed
		to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
		HART) as parent.

		riscv,num-ids:
		$ref: /schemas/types.yaml#/definitions/uint32
		minimum: 63
		maximum: 2047
		description:
		Number of interrupt identities supported by IMSIC interrupt file.

		riscv,num-guest-ids:
		$ref: /schemas/types.yaml#/definitions/uint32
		minimum: 63
		maximum: 2047
		description:
		Number of interrupt identities are supported by IMSIC guest interrupt
		file. When not specified it is assumed to be same as specified by the
		riscv,num-ids property.

		riscv,guest-index-bits:
		minimum: 0
		maximum: 7
		default: 0
		description:
		Number of guest index bits in the MSI target address.

		riscv,hart-index-bits:
		minimum: 0
		maximum: 15
		description:
		Number of HART index bits in the MSI target address. When not
		specified it is calculated based on the interrupts-extended property.

		riscv,group-index-bits:
		minimum: 0
		maximum: 7
		default: 0
		description:
		Number of group index bits in the MSI target address.

		riscv,group-index-shift:
		$ref: /schemas/types.yaml#/definitions/uint32
		minimum: 0
		maximum: 55
		default: 24
		description:
		The least significant bit position of the group index bits in the
		MSI target address.

		required:
		- compatible
		- reg
		- interrupt-controller
		- msi-controller
		- "#msi-cells"
		- interrupts-extended
		- riscv,num-ids

		unevaluatedProperties: false

		examples:
		- \|
		// Example 1 (Machine-level IMSIC files with just one group):

		interrupt-controller@24000000 {
		compatible = "qemu,imsics", "riscv,imsics";
		interrupts-extended = <&cpu1_intc 11>,
		<&cpu2_intc 11>,
		<&cpu3_intc 11>,
		<&cpu4_intc 11>;
		reg = <0x28000000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <0>;
		msi-controller;
		#msi-cells = <0>;
		riscv,num-ids = <127>;
		};

		- \|
		// Example 2 (Supervisor-level IMSIC files with two groups):

		interrupt-controller@28000000 {
		compatible = "qemu,imsics", "riscv,imsics";
		interrupts-extended = <&cpu1_intc 9>,
		<&cpu2_intc 9>,
		<&cpu3_intc 9>,
		<&cpu4_intc 9>;
		reg = <0x28000000 0x2000>, /* Group0 IMSICs */
		<0x29000000 0x2000>; /* Group1 IMSICs */
		interrupt-controller;
		#interrupt-cells = <0>;
		msi-controller;
		#msi-cells = <0>;
		riscv,num-ids = <127>;
		riscv,group-index-bits = <1>;
		riscv,group-index-shift = <24>;
		};
		...

Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml

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Original line number	Diff line number	Diff line
		@@ -89,8 +89,23 @@ examples:
		reg = <0x5000d000 0x400>;
		};

		- \|
		//Example 2
		exti2: interrupt-controller@40013c00 {
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		exti2: interrupt-controller@5000d000 {
		compatible = "st,stm32mp1-exti", "syscon";
		interrupt-controller;
		#interrupt-cells = <2>;
		reg = <0x5000d000 0x400>;
		interrupts-extended =
		<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		- \|
		//Example 3
		exti3: interrupt-controller@40013c00 {
		compatible = "st,stm32-exti";
		interrupt-controller;
		#interrupt-cells = <2>;

MAINTAINERS

+20 −0

Original line number	Diff line number	Diff line
		@@ -11454,6 +11454,7 @@ S: Maintained
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
		F: Documentation/core-api/irq/irq-domain.rst
		F: include/linux/irqdomain.h
		F: include/linux/irqdomain_defs.h
		F: kernel/irq/irqdomain.c
		F: kernel/irq/msi.c

		@@ -11463,6 +11464,10 @@ L: linux-kernel@vger.kernel.org
		S: Maintained
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
		F: include/linux/group_cpus.h
		F: include/linux/irq.h
		F: include/linux/irqhandler.h
		F: include/linux/irqnr.h
		F: include/linux/irqreturn.h
		F: kernel/irq/
		F: lib/group_cpus.c

		@@ -11473,6 +11478,7 @@ S: Maintained
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
		F: Documentation/devicetree/bindings/interrupt-controller/
		F: drivers/irqchip/
		F: include/linux/irqchip.h

		ISA
		M: William Breathitt Gray <william.gray@linaro.org>
		@@ -18974,6 +18980,20 @@ S: Maintained
		F: drivers/mtd/nand/raw/r852.c
		F: drivers/mtd/nand/raw/r852.h

		RISC-V AIA DRIVERS
		M: Anup Patel <anup@brainfault.org>
		L: linux-riscv@lists.infradead.org
		S: Maintained
		F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
		F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
		F: drivers/irqchip/irq-riscv-aplic-*.c
		F: drivers/irqchip/irq-riscv-aplic-*.h
		F: drivers/irqchip/irq-riscv-imsic-*.c
		F: drivers/irqchip/irq-riscv-imsic-*.h
		F: drivers/irqchip/irq-riscv-intc.c
		F: include/linux/irqchip/riscv-aplic.h
		F: include/linux/irqchip/riscv-imsic.h

		RISC-V ARCHITECTURE
		M: Paul Walmsley <paul.walmsley@sifive.com>
		M: Palmer Dabbelt <palmer@dabbelt.com>

arch/arm/boot/dts/st/stm32mp131.dtsi

+73 −1

Original line number	Diff line number	Diff line
		@@ -783,10 +783,82 @@ usb33: usb33 {
		};

		exti: interrupt-controller@5000d000 {
		compatible = "st,stm32mp13-exti", "syscon";
		compatible = "st,stm32mp1-exti", "syscon";
		interrupt-controller;
		#interrupt-cells = <2>;
		reg = <0x5000d000 0x400>;
		interrupts-extended =
		<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
		<&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
		<&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<0>,
		<&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
		<0>, /* EXTI_20 */
		<&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
		<&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>, /* EXTI_40 */
		<0>,
		<0>,
		<0>,
		<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<0>,
		<&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
		<0>,
		<&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
		<&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>, /* EXTI_60 */
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<0>,
		<&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
		<0>,
		<&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */
		};

		syscfg: syscon@50020000 {