Commit 6c42559f authored by Shashank Sharma's avatar Shashank Sharma Committed by Alex Deucher
Browse files

drm/amdgpu: map usermode queue into MES 



This patch adds new functions to map/unmap a usermode queue into
the FW, using the MES ring. As soon as this mapping is done, the
queue would  be considered ready to accept the workload.

V1: Addressed review comments from Alex on the RFC patch series
    - Map/Unmap should be IP specific.
V2:
    Addressed review comments from Christian:
    - Fix the wptr_mc_addr calculation (moved into another patch)
    Addressed review comments from Alex:
    - Do not add fptrs for map/unmap

V3:  Integration with doorbell manager
V4:  Rebase
V5:  Use gfx_v11_0 for function names (Alex)
V6:  Removed queue->proc/gang/fw_ctx_address variables and doing the
     address calculations locally to keep the queue structure GEN
     independent (Alex)
V7:  Added R-B from Alex
V8:  Rebase
V9:  Rebase
V10: Rebase

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent defb41e8

drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c

+74 −0
Original line number Diff line number Diff line
@@ -30,6 +30,69 @@ 
#define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE

#define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE



static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr,

			       struct amdgpu_usermode_queue *queue,

			       struct amdgpu_mqd_prop *userq_props)

{

	struct amdgpu_device *adev = uq_mgr->adev;

	struct amdgpu_userq_obj *ctx = &queue->fw_obj;

	struct mes_add_queue_input queue_input;

	int r;



	memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));



	queue_input.process_va_start = 0;

	queue_input.process_va_end = (adev->vm_manager.max_pfn - 1) << AMDGPU_GPU_PAGE_SHIFT;



	/* set process quantum to 10 ms and gang quantum to 1 ms as default */

	queue_input.process_quantum = 100000;

	queue_input.gang_quantum = 10000;

	queue_input.paging = false;



	queue_input.process_context_addr = ctx->gpu_addr;

	queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;

	queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;

	queue_input.gang_global_priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;



	queue_input.process_id = queue->vm->pasid;

	queue_input.queue_type = queue->queue_type;

	queue_input.mqd_addr = queue->mqd.gpu_addr;

	queue_input.wptr_addr = userq_props->wptr_gpu_addr;

	queue_input.queue_size = userq_props->queue_size >> 2;

	queue_input.doorbell_offset = userq_props->doorbell_index;

	queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo);



	amdgpu_mes_lock(&adev->mes);

	r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);

	amdgpu_mes_unlock(&adev->mes);

	if (r) {

		DRM_ERROR("Failed to map queue in HW, err (%d)\n", r);

		return r;

	}



	DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index);

	return 0;

}



static void mes_v11_0_userq_unmap(struct amdgpu_userq_mgr *uq_mgr,

				  struct amdgpu_usermode_queue *queue)

{

	struct amdgpu_device *adev = uq_mgr->adev;

	struct mes_remove_queue_input queue_input;

	struct amdgpu_userq_obj *ctx = &queue->fw_obj;

	int r;



	memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));

	queue_input.doorbell_offset = queue->doorbell_index;

	queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ;



	amdgpu_mes_lock(&adev->mes);

	r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);

	amdgpu_mes_unlock(&adev->mes);

	if (r)

		DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r);

}



static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,

					    struct amdgpu_usermode_queue *queue,

					    struct drm_amdgpu_userq_in *mqd_user)
@@ -105,8 +168,18 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 
		goto free_mqd;

	}



	/* Map userqueue into FW using MES */

	r = mes_v11_0_userq_map(uq_mgr, queue, userq_props);

	if (r) {

		DRM_ERROR("Failed to init MQD\n");

		goto free_ctx;

	}



	return 0;



free_ctx:

	amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj);



free_mqd:

	amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd);
@@ -120,6 +193,7 @@ static void 
mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr,

			    struct amdgpu_usermode_queue *queue)

{

	mes_v11_0_userq_unmap(uq_mgr, queue);

	amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj);

	kfree(queue->userq_prop);

	amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd);