Commit 6c52d4da authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma 

Pull rdma fixes from Jason Gunthorpe:

 - Put the QP netlink dump back in cxgb4, fixes a user visible
   regression

 - Don't change the rounding style in mlx5 for user provided rd_atomic
   values

 - Resolve a race in bnxt_re around the qp-handle table array

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma:
  RDMA/bnxt_re: synchronize the qp-handle table array
  RDMA/bnxt_re: Fix the usage of control path spin locks
  RDMA/mlx5: Round max_rd_atomic/max_dest_rd_atomic up instead of down
  RDMA/cxgb4: Dump vendor specific QP details
parents 5635f189 76d3ddff

drivers/infiniband/hw/bnxt_re/qplib_fp.c

+4 −0
Original line number Diff line number Diff line
@@ -1532,9 +1532,11 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, 
	u32 tbl_indx;

	int rc;



	spin_lock_bh(&rcfw->tbl_lock);

	tbl_indx = map_qp_id_to_tbl_indx(qp->id, rcfw);

	rcfw->qp_tbl[tbl_indx].qp_id = BNXT_QPLIB_QP_ID_INVALID;

	rcfw->qp_tbl[tbl_indx].qp_handle = NULL;

	spin_unlock_bh(&rcfw->tbl_lock);



	bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,

				 CMDQ_BASE_OPCODE_DESTROY_QP,
@@ -1545,8 +1547,10 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, 
				sizeof(resp), 0);

	rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);

	if (rc) {

		spin_lock_bh(&rcfw->tbl_lock);

		rcfw->qp_tbl[tbl_indx].qp_id = qp->id;

		rcfw->qp_tbl[tbl_indx].qp_handle = qp;

		spin_unlock_bh(&rcfw->tbl_lock);

		return rc;

	}

drivers/infiniband/hw/bnxt_re/qplib_rcfw.c

+19 −19
Original line number Diff line number Diff line
@@ -290,7 +290,6 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, 
	struct bnxt_qplib_hwq *hwq;

	u32 sw_prod, cmdq_prod;

	struct pci_dev *pdev;

	unsigned long flags;

	u16 cookie;

	u8 *preq;
@@ -301,7 +300,7 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, 
	/* Cmdq are in 16-byte units, each request can consume 1 or more

	 * cmdqe

	 */

	spin_lock_irqsave(&hwq->lock, flags);

	spin_lock_bh(&hwq->lock);

	required_slots = bnxt_qplib_get_cmd_slots(msg->req);

	free_slots = HWQ_FREE_SLOTS(hwq);

	cookie = cmdq->seq_num & RCFW_MAX_COOKIE_VALUE;
@@ -311,7 +310,7 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, 
		dev_info_ratelimited(&pdev->dev,

				     "CMDQ is full req/free %d/%d!",

				     required_slots, free_slots);

		spin_unlock_irqrestore(&hwq->lock, flags);

		spin_unlock_bh(&hwq->lock);

		return -EAGAIN;

	}

	if (msg->block)
@@ -367,7 +366,7 @@ static int __send_message(struct bnxt_qplib_rcfw *rcfw, 
	wmb();

	writel(cmdq_prod, cmdq->cmdq_mbox.prod);

	writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);

	spin_unlock_irqrestore(&hwq->lock, flags);

	spin_unlock_bh(&hwq->lock);

	/* Return the CREQ response pointer */

	return 0;

}
@@ -486,7 +485,6 @@ static int __bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 
{

	struct creq_qp_event *evnt = (struct creq_qp_event *)msg->resp;

	struct bnxt_qplib_crsqe *crsqe;

	unsigned long flags;

	u16 cookie;

	int rc;

	u8 opcode;
@@ -512,12 +510,12 @@ static int __bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw, 
		rc = __poll_for_resp(rcfw, cookie);



	if (rc) {

		spin_lock_irqsave(&rcfw->cmdq.hwq.lock, flags);

		spin_lock_bh(&rcfw->cmdq.hwq.lock);

		crsqe = &rcfw->crsqe_tbl[cookie];

		crsqe->is_waiter_alive = false;

		if (rc == -ENODEV)

			set_bit(FIRMWARE_STALL_DETECTED, &rcfw->cmdq.flags);

		spin_unlock_irqrestore(&rcfw->cmdq.hwq.lock, flags);

		spin_unlock_bh(&rcfw->cmdq.hwq.lock);

		return -ETIMEDOUT;

	}
@@ -628,7 +626,6 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 
	u16 cookie, blocked = 0;

	bool is_waiter_alive;

	struct pci_dev *pdev;

	unsigned long flags;

	u32 wait_cmds = 0;

	int rc = 0;
@@ -637,17 +634,21 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 
	case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:

		err_event = (struct creq_qp_error_notification *)qp_event;

		qp_id = le32_to_cpu(err_event->xid);

		spin_lock(&rcfw->tbl_lock);

		tbl_indx = map_qp_id_to_tbl_indx(qp_id, rcfw);

		qp = rcfw->qp_tbl[tbl_indx].qp_handle;

		if (!qp) {

			spin_unlock(&rcfw->tbl_lock);

			break;

		}

		bnxt_qplib_mark_qp_error(qp);

		rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);

		spin_unlock(&rcfw->tbl_lock);

		dev_dbg(&pdev->dev, "Received QP error notification\n");

		dev_dbg(&pdev->dev,

			"qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",

			qp_id, err_event->req_err_state_reason,

			err_event->res_err_state_reason);

		if (!qp)

			break;

		bnxt_qplib_mark_qp_error(qp);

		rc = rcfw->creq.aeq_handler(rcfw, qp_event, qp);

		break;

	default:

		/*
@@ -659,8 +660,7 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 
		 *

		 */



		spin_lock_irqsave_nested(&hwq->lock, flags,

					 SINGLE_DEPTH_NESTING);

		spin_lock_nested(&hwq->lock, SINGLE_DEPTH_NESTING);

		cookie = le16_to_cpu(qp_event->cookie);

		blocked = cookie & RCFW_CMD_IS_BLOCKING;

		cookie &= RCFW_MAX_COOKIE_VALUE;
@@ -672,7 +672,7 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 
			dev_info(&pdev->dev,

				 "rcfw timedout: cookie = %#x, free_slots = %d",

				 cookie, crsqe->free_slots);

			spin_unlock_irqrestore(&hwq->lock, flags);

			spin_unlock(&hwq->lock);

			return rc;

		}
@@ -720,7 +720,7 @@ static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw, 
			__destroy_timedout_ah(rcfw,

					      (struct creq_create_ah_resp *)

					      qp_event);

		spin_unlock_irqrestore(&hwq->lock, flags);

		spin_unlock(&hwq->lock);

	}

	*num_wait += wait_cmds;

	return rc;
@@ -734,12 +734,11 @@ static void bnxt_qplib_service_creq(struct tasklet_struct *t) 
	u32 type, budget = CREQ_ENTRY_POLL_BUDGET;

	struct bnxt_qplib_hwq *hwq = &creq->hwq;

	struct creq_base *creqe;

	unsigned long flags;

	u32 num_wakeup = 0;

	u32 hw_polled = 0;



	/* Service the CREQ until budget is over */

	spin_lock_irqsave(&hwq->lock, flags);

	spin_lock_bh(&hwq->lock);

	while (budget > 0) {

		creqe = bnxt_qplib_get_qe(hwq, hwq->cons, NULL);

		if (!CREQ_CMP_VALID(creqe, creq->creq_db.dbinfo.flags))
@@ -782,7 +781,7 @@ static void bnxt_qplib_service_creq(struct tasklet_struct *t) 
	if (hw_polled)

		bnxt_qplib_ring_nq_db(&creq->creq_db.dbinfo,

				      rcfw->res->cctx, true);

	spin_unlock_irqrestore(&hwq->lock, flags);

	spin_unlock_bh(&hwq->lock);

	if (num_wakeup)

		wake_up_nr(&rcfw->cmdq.waitq, num_wakeup);

}
@@ -978,6 +977,7 @@ int bnxt_qplib_alloc_rcfw_channel(struct bnxt_qplib_res *res, 
			       GFP_KERNEL);

	if (!rcfw->qp_tbl)

		goto fail;

	spin_lock_init(&rcfw->tbl_lock);



	rcfw->max_timeout = res->cctx->hwrm_cmd_max_timeout;

drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

+2 −0
Original line number Diff line number Diff line
@@ -224,6 +224,8 @@ struct bnxt_qplib_rcfw { 
	struct bnxt_qplib_crsqe		*crsqe_tbl;

	int qp_tbl_size;

	struct bnxt_qplib_qp_node *qp_tbl;

	/* To synchronize the qp-handle hash table */

	spinlock_t			tbl_lock;

	u64 oos_prev;

	u32 init_oos_stats;

	u32 cmdq_depth;

drivers/infiniband/hw/cxgb4/provider.c

+1 −0
Original line number Diff line number Diff line
@@ -473,6 +473,7 @@ static const struct ib_device_ops c4iw_dev_ops = { 
	.fill_res_cq_entry = c4iw_fill_res_cq_entry,

	.fill_res_cm_id_entry = c4iw_fill_res_cm_id_entry,

	.fill_res_mr_entry = c4iw_fill_res_mr_entry,

	.fill_res_qp_entry = c4iw_fill_res_qp_entry,

	.get_dev_fw_str = get_dev_fw_str,

	.get_dma_mr = c4iw_get_dma_mr,

	.get_hw_stats = c4iw_get_mib,

drivers/infiniband/hw/mlx5/qp.c

+2 −2
Original line number Diff line number Diff line
@@ -4268,14 +4268,14 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 
		MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);



	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)

		MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));

		MLX5_SET(qpc, qpc, log_sra_max, fls(attr->max_rd_atomic - 1));



	if (attr_mask & IB_QP_SQ_PSN)

		MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);



	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)

		MLX5_SET(qpc, qpc, log_rra_max,

			 ilog2(attr->max_dest_rd_atomic));

			 fls(attr->max_dest_rd_atomic - 1));



	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {

		err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);