Commit 6c605f44 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Port DENTIST hang and TDR fixes to OTG disable W/A 



[Why]
We can experience DENTIST hangs during optimize_bandwidth or TDRs if
FIFO is toggled and hangs.

[How]
Port the DCN35 fixes to DCN314.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 012fe067

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+9 −12
Original line number Diff line number Diff line
@@ -145,30 +145,27 @@ static int dcn314_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

				  bool safe_to_lower, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = safe_to_lower

			? &context->res_ctx.pipe_ctx[i]

			: &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;

		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {

			struct stream_encoder *stream_enc = pipe->stream_res.stream_enc;



			if (disable) {

				if (stream_enc && stream_enc->funcs->disable_fifo)

					pipe->stream_res.stream_enc->funcs->disable_fifo(stream_enc);



				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);



				reset_sync_context_for_pipe(dc, context, i);

			} else {

				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);



				if (stream_enc && stream_enc->funcs->enable_fifo)

					pipe->stream_res.stream_enc->funcs->enable_fifo(stream_enc);

			}

		}

	}
@@ -297,11 +294,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn314_disable_otg_wa(clk_mgr_base, context, true);

		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn314_disable_otg_wa(clk_mgr_base, context, false);

		dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);



		update_dispclk = true;

	}