Commit 6c735383 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: add missing CAN bus clocks 



The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a
CAN bus clock. The bus clock was omitted when the binding was written,
but is required for operation. Make up for lost time and add to the DT.

Fixes: 38a71fc0 ("riscv: dts: microchip: add mpfs's CAN controllers")
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 2db68ddb

arch/riscv/boot/dts/microchip/mpfs.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ i2c1: i2c@2010b000 { 
		can0: can@2010c000 {

			compatible = "microchip,mpfs-can";

			reg = <0x0 0x2010c000 0x0 0x1000>;

			clocks = <&clkcfg CLK_CAN0>;

			clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <56>;

			status = "disabled";
@@ -431,7 +431,7 @@ can0: can@2010c000 { 
		can1: can@2010d000 {

			compatible = "microchip,mpfs-can";

			reg = <0x0 0x2010d000 0x0 0x1000>;

			clocks = <&clkcfg CLK_CAN1>;

			clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <57>;

			status = "disabled";