Commit 6ca00ec4 authored by Akiva Goldberger's avatar Akiva Goldberger Committed by Leon Romanovsky
Browse files

net/mlx5: Add nic_cap_reg and vhca_icm_ctrl registers 



Add nic_cap_reg and vhca_icm_ctrl registers interfaces for exposing ICM
consumption.

Signed-off-by: default avatarAkiva Goldberger <agoldberger@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20250109204231.1809851-5-tariqt@nvidia.com


Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Reviewed-by: default avatarKalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent df75ad56

include/linux/mlx5/driver.h

+2 −0
Original line number Diff line number Diff line
@@ -163,7 +163,9 @@ enum { 
	MLX5_REG_MRTCQ		 = 0x9182,

	MLX5_REG_SBCAM		 = 0xB01F,

	MLX5_REG_RESOURCE_DUMP   = 0xC000,

	MLX5_REG_NIC_CAP	 = 0xC00D,

	MLX5_REG_DTOR            = 0xC00E,

	MLX5_REG_VHCA_ICM_CTRL	 = 0xC010,

};



enum mlx5_qpts_trust_state {

include/linux/mlx5/mlx5_ifc.h

+21 −1
Original line number Diff line number Diff line
@@ -1830,7 +1830,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { 
	u8         regexp_params[0x1];

	u8         uar_sz[0x6];

	u8         port_selection_cap[0x1];

	u8         reserved_at_251[0x1];

	u8         nic_cap_reg[0x1];

	u8         umem_uid_0[0x1];

	u8         reserved_at_253[0x5];

	u8         log_pg_sz[0x8];
@@ -3327,6 +3327,14 @@ struct mlx5_ifc_dropped_packet_logged_bits { 
	u8         reserved_at_0[0xe0];

};



struct mlx5_ifc_nic_cap_reg_bits {

	u8	   reserved_at_0[0x1a];

	u8	   vhca_icm_ctrl[0x1];

	u8	   reserved_at_1b[0x5];



	u8	   reserved_at_20[0x60];

};



struct mlx5_ifc_default_timeout_bits {

	u8         to_multiplier[0x3];

	u8         reserved_at_3[0x9];
@@ -3363,6 +3371,18 @@ struct mlx5_ifc_dtor_reg_bits { 
	u8         reserved_at_1c0[0x20];

};



struct mlx5_ifc_vhca_icm_ctrl_reg_bits {

	u8	   vhca_id_valid[0x1];

	u8	   reserved_at_1[0xf];

	u8	   vhca_id[0x10];



	u8	   reserved_at_20[0xa0];



	u8	   cur_alloc_icm[0x20];



	u8	   reserved_at_e0[0x120];

};



enum {

	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,

	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,