Commit 6cb8c1f9 authored by Stephan Gerhold's avatar Stephan Gerhold Committed by Vinod Koul
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phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmware 



Commit 0cc22f5a ("phy: qcom: qmp-pcie: Add PHY register retention
support") added support for using the "no_csr" reset to skip configuration
of the PHY if the init sequence was already applied by the boot firmware.
The expectation is that the PHY is only turned on/off by using the "no_csr"
reset, instead of powering it down and re-programming it after a full
reset.

The boot firmware on X1E does not fully conform to this expectation: If the
PCIe3 link fails to come up (e.g. because no PCIe card is inserted), the
firmware powers down the PHY using the QPHY_PCS_POWER_DOWN_CONTROL
register. The QPHY_START_CTRL register is kept as-is, so the driver assumes
the PHY is already initialized and skips the configuration/power up
sequence. The PHY won't come up again without clearing the
QPHY_PCS_POWER_DOWN_CONTROL, so eventually initialization fails:

  qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
  phy phy-1be0000.phy.0: phy poweron failed --> -110
  qcom-pcie 1bd0000.pcie: cannot initialize host
  qcom-pcie 1bd0000.pcie: probe with driver qcom-pcie failed with error -110

This can be reliably reproduced on the X1E CRD, QCP and Devkit when no card
is inserted for PCIe3.

Fix this by checking the QPHY_PCS_POWER_DOWN_CONTROL register in addition
to QPHY_START_CTRL. If the PHY is powered down with the register, it
doesn't conform to the expectations for using the "no_csr" reset, so we
fully re-initialize with the normal reset sequence.

Also check the register more carefully to ensure all of the bits we expect
are actually set. A simple !!(readl()) is not enough, because the PHY might
be only partially set up with some of the expected bits set.

Cc: stable@vger.kernel.org
Fixes: 0cc22f5a ("phy: qcom: qmp-pcie: Add PHY register retention support")
Signed-off-by: default avatarStephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250821-phy-qcom-qmp-pcie-nocsr-fix-v3-1-4898db0cc07c@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a22d3b0d

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+19 −6
Original line number Diff line number Diff line
@@ -3067,6 +3067,14 @@ struct qmp_pcie { 
	struct clk_fixed_rate aux_clk_fixed;

};



static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)

{

	u32 reg;



	reg = readl(base + offset);

	return (reg & val) == val;

}



static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)

{

	u32 reg;
@@ -4339,16 +4347,21 @@ static int qmp_pcie_init(struct phy *phy) 
	struct qmp_pcie *qmp = phy_get_drvdata(phy);

	const struct qmp_phy_cfg *cfg = qmp->cfg;

	void __iomem *pcs = qmp->pcs;

	bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));

	int ret;



	qmp->skip_init = qmp->nocsr_reset && phy_initialized;

	/*

	 * We need to check the existence of init sequences in two cases:

	 * 1. The PHY doesn't support no_csr reset.

	 * 2. The PHY supports no_csr reset but isn't initialized by bootloader.

	 * As we can't skip init in these two cases.

	 * We can skip PHY initialization if all of the following conditions

	 * are met:

	 *  1. The PHY supports the nocsr_reset that preserves the PHY config.

	 *  2. The PHY was started (and not powered down again) by the

	 *     bootloader, with all of the expected bits set correctly.

	 * In this case, we can continue without having the init sequence

	 * defined in the driver.

	 */

	qmp->skip_init = qmp->nocsr_reset &&

		qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) &&

		qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl);



	if (!qmp->skip_init && !cfg->tbls.serdes_num) {

		dev_err(qmp->dev, "Init sequence not available\n");

		return -ENODATA;