Commit 6cf96df7 authored by Jaewon Kim's avatar Jaewon Kim Committed by Krzysztof Kozlowski
Browse files

pinctrl: samsung: add exynosautov920 pinctrl 



Add pinctrl data for ExynosAutov920 SoC.
It has a newly applied pinctrl register layer for ExynosAuto series.

Pinctrl data for ExynosAutoV920 SoC.
 - GPA0,GPA1 (10): External wake up interrupt
 - GPQ0 (2): SPMI (PMIC I/F)
 - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio
 - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet
 - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose
 - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI

Signed-off-by: default avatarJaewon Kim <jaewon02.kim@samsung.com>
Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 884fdaa5

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

+140 −0
Original line number Diff line number Diff line
@@ -726,6 +726,146 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { 
	.num_ctrl	= ARRAY_SIZE(exynosautov9_pin_ctrl),

};



/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {

	EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),

	EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),

};



/* pin banks of exynosautov920 pin-controller 1 (AUD) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {

	EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),

};



/* pin banks of exynosautov920 pin-controller 2 (HSI0) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {

	EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),

};



/* pin banks of exynosautov920 pin-controller 3 (HSI1) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {

	EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),

};



/* pin banks of exynosautov920 pin-controller 4 (HSI2) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {

	EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),

};



/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {

	EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),

};



/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {

	EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),

};



/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */

static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {

	EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5",  0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6",  0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7",  0x18, 0x24, 0x28),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8",  0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9",  0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),

	EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1",  0x18, 0x24, 0x28),

};



static const struct samsung_retention_data exynosautov920_retention_data __initconst = {

	.regs	 = NULL,

	.nr_regs = 0,

	.value	 = 0,

	.refcnt	 = &exynos_shared_retention_refcnt,

	.init	 = exynos_retention_init,

};



static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {

	{

		/* pin-controller instance 0 ALIVE data */

		.pin_banks	= exynosautov920_pin_banks0,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks0),

		.eint_wkup_init	= exynos_eint_wkup_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

		.retention_data	= &exynosautov920_retention_data,

	}, {

		/* pin-controller instance 1 AUD data */

		.pin_banks	= exynosautov920_pin_banks1,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks1),

	}, {

		/* pin-controller instance 2 HSI0 data */

		.pin_banks	= exynosautov920_pin_banks2,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks2),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 3 HSI1 data */

		.pin_banks	= exynosautov920_pin_banks3,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks3),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 4 HSI2 data */

		.pin_banks	= exynosautov920_pin_banks4,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks4),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 5 HSI2UFS data */

		.pin_banks	= exynosautov920_pin_banks5,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks5),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 6 PERIC0 data */

		.pin_banks	= exynosautov920_pin_banks6,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks6),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	}, {

		/* pin-controller instance 7 PERIC1 data */

		.pin_banks	= exynosautov920_pin_banks7,

		.nr_banks	= ARRAY_SIZE(exynosautov920_pin_banks7),

		.eint_gpio_init	= exynos_eint_gpio_init,

		.suspend	= exynos_pinctrl_suspend,

		.resume		= exynos_pinctrl_resume,

	},

};



const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {

	.ctrl		= exynosautov920_pin_ctrl,

	.num_ctrl	= ARRAY_SIZE(exynosautov920_pin_ctrl),

};



/*

 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three

 * gpio/pin-mux/pinconfig controllers.

drivers/pinctrl/samsung/pinctrl-exynos.c

+22 −1
Original line number Diff line number Diff line
@@ -281,6 +281,9 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 
	unsigned int svc, group, pin;

	int ret;



	if (bank->eint_con_offset)

		svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);

	else

		svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);

	group = EXYNOS_SVC_GROUP(svc);

	pin = svc & EXYNOS_SVC_NUM_MASK;
@@ -490,6 +493,22 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { 
	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,

};



static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {

	.chip = {

		.name = "exynosautov920_wkup_irq_chip",

		.irq_unmask = exynos_irq_unmask,

		.irq_mask = exynos_irq_mask,

		.irq_ack = exynos_irq_ack,

		.irq_set_type = exynos_irq_set_type,

		.irq_set_wake = exynos_wkup_irq_set_wake,

		.irq_request_resources = exynos_irq_request_resources,

		.irq_release_resources = exynos_irq_release_resources,

	},

	.eint_wake_mask_value = &eint_wake_mask_value,

	.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,

	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,

};



/* list of external wakeup controllers supported */

static const struct of_device_id exynos_wkup_irq_ids[] = {

	{ .compatible = "samsung,s5pv210-wakeup-eint",
@@ -502,6 +521,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { 
			.data = &exynos7_wkup_irq_chip },

	{ .compatible = "samsung,exynosautov9-wakeup-eint",

			.data = &exynos7_wkup_irq_chip },

	{ .compatible = "samsung,exynosautov920-wakeup-eint",

			.data = &exynosautov920_wkup_irq_chip },

	{ }

};

drivers/pinctrl/samsung/pinctrl-exynos.h

+25 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define EXYNOS7_WKUP_EMASK_OFFSET	0x900

#define EXYNOS7_WKUP_EPEND_OFFSET	0xA00

#define EXYNOS_SVC_OFFSET		0xB08

#define EXYNOSAUTO_SVC_OFFSET		0xF008



/* helpers to access interrupt service register */

#define EXYNOS_SVC_GROUP_SHIFT		3
@@ -140,6 +141,30 @@ 
		.name		= id				\

	}



#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs)	\

	{							\

		.type			= &exynos850_bank_type_off,	\

		.pctl_offset		= reg,				\

		.nr_pins		= pins,				\

		.eint_type		= EINT_TYPE_GPIO,		\

		.eint_con_offset	= con_offs,			\

		.eint_mask_offset	= mask_offs,			\

		.eint_pend_offset	= pend_offs,			\

		.name			= id				\

	}



#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs)	\

	{							\

		.type			= &exynos850_bank_type_alive,	\

		.pctl_offset		= reg,				\

		.nr_pins		= pins,				\

		.eint_type		= EINT_TYPE_WKUP,		\

		.eint_con_offset	= con_offs,			\

		.eint_mask_offset	= mask_offs,			\

		.eint_pend_offset	= pend_offs,			\

		.name			= id				\

	}



/**

 * struct exynos_weint_data: irq specific data for all the wakeup interrupts

 * generated by the external wakeup interrupt controller.

drivers/pinctrl/samsung/pinctrl-samsung.c

+2 −0
Original line number Diff line number Diff line
@@ -1324,6 +1324,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { 
		.data = &exynos850_of_data },

	{ .compatible = "samsung,exynosautov9-pinctrl",

		.data = &exynosautov9_of_data },

	{ .compatible = "samsung,exynosautov920-pinctrl",

		.data = &exynosautov920_of_data },

	{ .compatible = "tesla,fsd-pinctrl",

		.data = &fsd_of_data },

#endif

drivers/pinctrl/samsung/pinctrl-samsung.h

+1 −0
Original line number Diff line number Diff line
@@ -362,6 +362,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; 
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;

extern const struct samsung_pinctrl_of_match_data exynos850_of_data;

extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;

extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;

extern const struct samsung_pinctrl_of_match_data fsd_of_data;

extern const struct samsung_pinctrl_of_match_data gs101_of_data;

extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;