Unverified Commit 6d1a6f46 authored by Vincent Chen's avatar Vincent Chen Committed by Palmer Dabbelt
Browse files

rseq/selftests: Add support for RISC-V 



Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.

Signed-off-by: default avatarVincent Chen <vincent.chen@sifive.com>
Tested-by: default avatarEric Lin <eric.lin@sifive.com>
Reviewed-by: default avatarMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 93917ad5

tools/testing/selftests/rseq/param_test.c

+23 −0
Original line number Diff line number Diff line
@@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; 
	"addiu " INJECT_ASM_REG ", -1\n\t" \

	"bnez " INJECT_ASM_REG ", 222b\n\t" \

	"333:\n\t"

#elif defined(__riscv)



#define RSEQ_INJECT_INPUT \

	, [loop_cnt_1]"m"(loop_cnt[1]) \

	, [loop_cnt_2]"m"(loop_cnt[2]) \

	, [loop_cnt_3]"m"(loop_cnt[3]) \

	, [loop_cnt_4]"m"(loop_cnt[4]) \

	, [loop_cnt_5]"m"(loop_cnt[5]) \

	, [loop_cnt_6]"m"(loop_cnt[6])



#define INJECT_ASM_REG	"t1"



#define RSEQ_INJECT_CLOBBER \

	, INJECT_ASM_REG



#define RSEQ_INJECT_ASM(n)					\

	"lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t"		\

	"beqz " INJECT_ASM_REG ", 333f\n\t"			\

	"222:\n\t"						\

	"addi  " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t"	\

	"bnez " INJECT_ASM_REG ", 222b\n\t"			\

	"333:\n\t"





#else

#error unsupported target

tools/testing/selftests/rseq/rseq-riscv.h

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+677 −0

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tools/testing/selftests/rseq/rseq.h

+2 −0
Original line number Diff line number Diff line
@@ -79,6 +79,8 @@ extern int __rseq_handled; 
#include <rseq-mips.h>

#elif defined(__s390__)

#include <rseq-s390.h>

#elif defined(__riscv)

#include <rseq-riscv.h>

#else

#error unsupported target

#endif