Commit 6d2191d2 authored by Ellen Pan's avatar Ellen Pan Committed by Alex Deucher
Browse files

drm/amdgpu: Add SRIOV crit_region_version support 



1. Added enum amd_sriov_crit_region_version to support multi versions
2. Added logic in SRIOV mailbox to regonize crit_region version during
   req_gpu_init_data

Signed-off-by: default avatarEllen Pan <yunru.pan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d88c8bec

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+3 −2
Original line number Diff line number Diff line
@@ -150,9 +150,10 @@ void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 
		virt->ops->req_init_data(adev);



	if (adev->virt.req_init_data_ver > 0)

		DRM_INFO("host supports REQ_INIT_DATA handshake\n");

		dev_info(adev->dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n",

				 adev->virt.req_init_data_ver);

	else

		DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");

		dev_warn(adev->dev, "host doesn't support REQ_INIT_DATA handshake\n");

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+8 −0
Original line number Diff line number Diff line
@@ -262,6 +262,11 @@ struct amdgpu_virt_ras { 


DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST);



struct amdgpu_virt_region {

	uint32_t offset;

	uint32_t size_kb;

};



/* GPU virtualization */

struct amdgpu_virt {

	uint32_t			caps;
@@ -289,6 +294,9 @@ struct amdgpu_virt { 
	bool ras_init_done;

	uint32_t reg_access;



	/* dynamic(v2) critical regions */

	struct amdgpu_virt_region init_data_header;



	/* vf2pf message */

	struct delayed_work vf2pf_work;

	uint32_t vf2pf_update_interval_ms;

drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h

+5 −0
Original line number Diff line number Diff line
@@ -66,6 +66,11 @@ 
	(AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \

	 AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1)



enum amd_sriov_crit_region_version {

	GPU_CRIT_REGION_V1 = 1,

	GPU_CRIT_REGION_V2 = 2,

};



/*

 * PF2VF history log:

 * v1 defined in amdgim

drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c

+16 −7
Original line number Diff line number Diff line
@@ -222,12 +222,20 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, 
				adev->virt.req_init_data_ver = 0;

		} else {

			if (req == IDH_REQ_GPU_INIT_DATA) {

				adev->virt.req_init_data_ver =

					RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1);



				/* assume V1 in case host doesn't set version number */

				if (adev->virt.req_init_data_ver < 1)

					adev->virt.req_init_data_ver = 1;

				switch (RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1)) {

				case GPU_CRIT_REGION_V2:

					adev->virt.req_init_data_ver = GPU_CRIT_REGION_V2;

					adev->virt.init_data_header.offset =

						RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2);

					adev->virt.init_data_header.size_kb =

						RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW3);

					break;

				default:

					adev->virt.req_init_data_ver = GPU_CRIT_REGION_V1;

					adev->virt.init_data_header.offset = -1;

					adev->virt.init_data_header.size_kb = 0;

					break;

				}

			}

		}
@@ -285,7 +293,8 @@ static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev, 


static int xgpu_nv_request_init_data(struct amdgpu_device *adev)

{

	return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA);

	return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_GPU_INIT_DATA,

			0, GPU_CRIT_REGION_V2, 0);

}



static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev,