Commit 6d2f913f authored by Yushan Wang's avatar Yushan Wang Committed by Will Deacon
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Documentation: hisi-pmu: Add introduction to HiSilicon V3 PMU 



Some of HiSilicon V3 PMU hardware is divided into parts to fulfill the
job of monitoring specific parts of a device.  Add description on that
as well as the newly added ext option for L3C PMU.

Acked-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: default avatarYushan Wang <wangyushan12@huawei.com>
Reviewed-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 272dd0e5

Documentation/admin-guide/perf/hisi-pmu.rst

+33 −0
Original line number Diff line number Diff line
@@ -124,6 +124,39 @@ channel with this option. The current supported channels are as follows: 
7. tt_en: NoC PMU supports counting only transactions that have tracetag set

if this option is set. See the 2nd list for more information about tracetag.



For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are

further divided into parts for finer granularity of tracing, each part has its

own dedicated PMU, and all such PMUs together cover the monitoring job of events

on particular uncore device. Such PMUs are described in sysfs with name format

slightly changed::



/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>



Z is the sub-id, indicating different PMUs for part of hardware device.



Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU

provides ``ext`` option to allow exploration of even finer granual statistics

of L3C PMU.  L3C PMU driver uses that as hint of termination when delivering

perf command to hardware:



- ext=0: Default, could be used with event names.

- ext=1 and ext=2: Must be used with event codes, event names are not supported.



An example of perf command could be::



  $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5



or::



  $# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5



As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1

pipe0.



First command locates the first part of L3C since ``ext=0`` is implied by

default. Second command issues the counting on another part of L3C with the

event ``0x1``.



Users could configure IDs to count data come from specific CCL/ICL, by setting

srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting

tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not