Commit 6d3e2ce6 authored by Srinivas Pandruvada's avatar Srinivas Pandruvada Committed by Rafael J. Wysocki
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thermal: intel: int340x: Read DDR data rate for Nova Lake 



Add support for reading DDR data rate from PCI config offset.

The register details are:

 CFG Offset : 0xE0
 Bits	   : 11:2

DDR Data rate is in 33.33 MTPS units.

Signed-off-by: default avatarSrinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Rearrange code to avoid using goto and make declarations consistent ]
Link: https://patch.msgid.link/20260223190420.874853-1-srinivas.pandruvada@linux.intel.com


Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 11439c46

drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

+20 −5
Original line number Diff line number Diff line
@@ -402,17 +402,31 @@ static ssize_t rfi_restriction_show(struct device *dev, 
	return sysfs_emit(buf, "%llu\n", resp);

}



 /* ddr_data_rate */

static const struct mmio_reg nvl_ddr_data_rate_reg = { 1, 0xE0, 10, 0x3FF, 2};



static const struct mmio_reg *ddr_data_rate_reg;



static ssize_t ddr_data_rate_show(struct device *dev,

				  struct device_attribute *attr,

				  char *buf)

{

	u16 id = 0x0107;

	u64 resp;



	if (ddr_data_rate_reg) {

		u16 reg_val;



		pci_read_config_word(to_pci_dev(dev), ddr_data_rate_reg->offset, &reg_val);

		resp = (reg_val >> ddr_data_rate_reg->shift) & ddr_data_rate_reg->mask;

		resp = (resp * 3333) / 100;

	} else {

		const u16 id = 0x0107;

		int ret;



		ret = processor_thermal_send_mbox_read_cmd(to_pci_dev(dev), id, &resp);

		if (ret)

			return ret;

	}



	return sysfs_emit(buf, "%llu\n", resp);

}
@@ -461,6 +475,7 @@ int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc 
		case PCI_DEVICE_ID_INTEL_NVL_H_THERMAL:

		case PCI_DEVICE_ID_INTEL_NVL_S_THERMAL:

			dlvr_mmio_regs_table = nvl_dlvr_mmio_regs;

			ddr_data_rate_reg = &nvl_ddr_data_rate_reg;

			break;

		default:

			dlvr_mmio_regs_table = dlvr_mmio_regs;