Commit 6d837271 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2024-04-11' of https://gitlab.freedesktop.org/drm/msm into drm-fixes 



Fixes for v6.9

Display:
- Fixes for PM refcount leak when DP goes to disconnected state and
  also when link training fails. This is also one of the issues found
  with the pm runtime series
- Add missing newlines to prints in msm_fb and msm_kms
- Change permissions of some dpu debugfs entries which write to const
  data from catalog to read-only to avoid protection faults
- Fix the interface table for the catalog of X1E80100. This is an
  important fix to bringup DP for X1E80100.
- Logging fix to print the callback symbol in the invalid IRQ message
  case rather than printing when its known to be NULL.
- Bindings fix to add DP node as child of mdss for mdss node
- Minor typo fix in DP driver API which handles port status change

GPU:
- fix CHRASHDUMP_READ()
- fix HHB (highest bank bit) for a619 to fix UBWC corruption

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvFwRUcHGWva7oDeydq1PTiZMduuykCD2MWaFrT4iMGZA@mail.gmail.com
parents 1bafeaf2 9dc23cba

Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml

+9 −0
Original line number Diff line number Diff line
@@ -53,6 +53,15 @@ patternProperties: 
      compatible:

        const: qcom,sm8150-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true



    properties:

      compatible:

        contains:

          const: qcom,sm8150-dp



  "^dsi@[0-9a-f]+$":

    type: object

    additionalProperties: true

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+4 −0
Original line number Diff line number Diff line
@@ -1377,6 +1377,10 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	if (adreno_is_a618(gpu))

		gpu->ubwc_config.highest_bank_bit = 14;



	if (adreno_is_a619(gpu))

		/* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */

		gpu->ubwc_config.highest_bank_bit = 13;



	if (adreno_is_a619_holi(gpu))

		gpu->ubwc_config.highest_bank_bit = 13;

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+1 −1
Original line number Diff line number Diff line
@@ -852,7 +852,7 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu, 
			(block->type << 8) | i);



		in += CRASHDUMP_READ(in, REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE,

			block->size, dumper->iova + A6XX_CD_DATA_OFFSET);

			block->size, out);



		out += block->size * sizeof(u32);

	}

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h

+31 −3
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { 
	},

};



/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */

static const struct dpu_intf_cfg x1e80100_intf[] = {

	{

		.name = "intf_0", .id = INTF_0,
@@ -358,8 +359,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { 
		.name = "intf_3", .id = INTF_3,

		.base = 0x37000, .len = 0x280,

		.features = INTF_SC7280_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.type = INTF_NONE,

		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
@@ -368,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { 
		.base = 0x38000, .len = 0x280,

		.features = INTF_SC7280_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_2,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
@@ -381,6 +382,33 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { 
		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),

	}, {

		.name = "intf_6", .id = INTF_6,

		.base = 0x3A000, .len = 0x280,

		.features = INTF_SC7280_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_2,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),

	}, {

		.name = "intf_7", .id = INTF_7,

		.base = 0x3b000, .len = 0x280,

		.features = INTF_SC7280_MASK,

		.type = INTF_NONE,

		.controller_id = MSM_DP_CONTROLLER_2,	/* pair with intf_6 for DP MST */

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),

	}, {

		.name = "intf_8", .id = INTF_8,

		.base = 0x3c000, .len = 0x280,

		.features = INTF_SC7280_MASK,

		.type = INTF_NONE,

		.controller_id = MSM_DP_CONTROLLER_1,	/* pair with intf_4 for DP MST */

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),

	},

};

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

+5 −5
Original line number Diff line number Diff line
@@ -459,15 +459,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) 
			&perf->core_clk_rate);

	debugfs_create_u32("enable_bw_release", 0600, entry,

			(u32 *)&perf->enable_bw_release);

	debugfs_create_u32("threshold_low", 0600, entry,

	debugfs_create_u32("threshold_low", 0400, entry,

			(u32 *)&perf->perf_cfg->max_bw_low);

	debugfs_create_u32("threshold_high", 0600, entry,

	debugfs_create_u32("threshold_high", 0400, entry,

			(u32 *)&perf->perf_cfg->max_bw_high);

	debugfs_create_u32("min_core_ib", 0600, entry,

	debugfs_create_u32("min_core_ib", 0400, entry,

			(u32 *)&perf->perf_cfg->min_core_ib);

	debugfs_create_u32("min_llcc_ib", 0600, entry,

	debugfs_create_u32("min_llcc_ib", 0400, entry,

			(u32 *)&perf->perf_cfg->min_llcc_ib);

	debugfs_create_u32("min_dram_ib", 0600, entry,

	debugfs_create_u32("min_dram_ib", 0400, entry,

			(u32 *)&perf->perf_cfg->min_dram_ib);

	debugfs_create_file("perf_mode", 0600, entry,

			(u32 *)perf, &dpu_core_perf_mode_fops);