Commit 6dad43bb authored by Eric Lin's avatar Eric Lin Committed by Namhyung Kim
Browse files

perf vendor events riscv: Add SiFive P650 events 



The SiFive Performance P650 core (including the vector-enabled P670 and
area-optimized P450/P470 variants) updates the P550 microarchitecture.
It brings in the debug, trace, and counter events from newer Bullet
cores, and adds new events for iTLB and dTLB multi-hits.

All other PMU events are unchanged from the P550 core.

Signed-off-by: default avatarEric Lin <eric.lin@sifive.com>
Co-developed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Signed-off-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Tested-by: default avatarIan Rogers <irogers@google.com>
Tested-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-8-samuel.holland@sifive.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 2e3a13d6

tools/perf/pmu-events/arch/riscv/mapfile.csv

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@@ -18,6 +18,7 @@ 
0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core

0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core

0x489-0x8000000000000008-0x[[:xdigit:]]+,v1,sifive/p550,core

0x489-0x8000000000000[1-6]08-0x[9b][[:xdigit:]]+,v1,sifive/p650,core

0x5b7-0x0-0x0,v1,thead/c900-legacy,core

0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core

0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core

tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json

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../bullet-07/cycle-and-instruction-count.json
 
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tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json

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../bullet/firmware.json
 
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tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json

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../bullet/instruction.json
 
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tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json

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[

  {

    "EventName": "ICACHE_MISS",

    "EventCode": "0x102",

    "BriefDescription": "Counts instruction cache misses"

  },

  {

    "EventName": "DCACHE_MISS",

    "EventCode": "0x202",

    "BriefDescription": "Counts data cache misses"

  },

  {

    "EventName": "DCACHE_RELEASE",

    "EventCode": "0x402",

    "BriefDescription": "Counts writeback requests from the data cache"

  },

  {

    "EventName": "ITLB_MISS",

    "EventCode": "0x802",

    "BriefDescription": "Counts Instruction TLB misses caused by instruction address translation requests"

  },

  {

    "EventName": "DTLB_MISS",

    "EventCode": "0x1002",

    "BriefDescription": "Counts Data TLB misses caused by data address translation requests"

  },

  {

    "EventName": "UTLB_MISS",

    "EventCode": "0x2002",

    "BriefDescription": "Counts Unified TLB misses caused by address translation requests"

  },

  {

    "EventName": "UTLB_HIT",

    "EventCode": "0x4002",

    "BriefDescription": "Counts Unified TLB hits for address translation requests"

  },

  {

    "EventName": "PTE_CACHE_MISS",

    "EventCode": "0x8002",

    "BriefDescription": "Counts Page Table Entry cache misses"

  },

  {

    "EventName": "PTE_CACHE_HIT",

    "EventCode": "0x10002",

    "BriefDescription": "Counts Page Table Entry cache hits"

  },

  {

    "EventName": "ITLB_MULTI_HIT",

    "EventCode": "0x20002",

    "BriefDescription": "Counts Instruction TLB multi-hits"

  },

  {

    "EventName": "DTLB_MULTI_HIT",

    "EventCode": "0x40002",

    "BriefDescription": "Counts Data TLB multi-hits"

  }

]