Commit 6dbe3c54 authored by Niravkumar L Rabara's avatar Niravkumar L Rabara Committed by Borislav Petkov (AMD)
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EDAC/altera: Set DDR and SDMMC interrupt mask before registration 



Mask DDR and SDMMC in probe function to avoid spurious interrupts before
registration.  Removed invalid register write to system manager.

Fixes: 1166fde9 ("EDAC, altera: Add Arria10 ECC memory init functions")
Signed-off-by: default avatarNiravkumar L Rabara <niravkumar.l.rabara@altera.com>
Signed-off-by: default avatarMatthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Cc: stable@kernel.org
Link: https://lore.kernel.org/20250425142640.33125-3-matthew.gerlach@altera.com
parent 4fb7b8fc

drivers/edac/altera_edac.c

+4 −3
Original line number Diff line number Diff line
@@ -1005,9 +1005,6 @@ altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 
		}

	}



	/* Interrupt mode set to every SBERR */

	regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,

		     ALTR_A10_ECC_INTMODE);

	/* Enable ECC */

	ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +

					ALTR_A10_ECC_CTRL_OFST));
@@ -2127,6 +2124,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev) 
		return PTR_ERR(edac->ecc_mgr_map);

	}



	/* Set irq mask for DDR SBE to avoid any pending irq before registration */

	regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,

		     (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));



	edac->irq_chip.name = pdev->dev.of_node->name;

	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;

	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;

drivers/edac/altera_edac.h

+2 −0
Original line number Diff line number Diff line
@@ -249,6 +249,8 @@ struct altr_sdram_mc_data { 
#define A10_SYSMGR_ECC_INTMASK_SET_OFST   0x94

#define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98

#define A10_SYSMGR_ECC_INTMASK_OCRAM      BIT(1)

#define A10_SYSMGR_ECC_INTMASK_SDMMCB     BIT(16)

#define A10_SYSMGR_ECC_INTMASK_DDR0       BIT(17)



#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST  0x9C

#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0