Commit 6dddc1eb authored by Candice Li's avatar Candice Li Committed by Alex Deucher
Browse files

drm/amdgpu: Update umc v8_10_0 headers 



Add GeccCtrl offset and mask to umc v8_10_0 headers.

Signed-off-by: default avatarCandice Li <candice.li@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 38dbbfa5

drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -29,5 +29,7 @@ 
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX  2

#define regMCA_UMC_UMC0_MCUMC_ADDRT0             0x03c4

#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX    2

#define regUMCCH0_0_GeccCtrl                     0x0053

#define regUMCCH0_0_GeccCtrl_BASE_IDX            2



#endif

drivers/gpu/drm/amd/include/asic_reg/umc/umc_8_10_0_sh_mask.h

+3 −0
Original line number Diff line number Diff line
@@ -90,5 +90,8 @@ 
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT        0x0

#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT         0x38

#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK          0x00FFFFFFFFFFFFFFL

//UMCCH0_0_GeccCtrl

#define UMCCH0_0_GeccCtrl__UCFatalEn__SHIFT                0xd

#define UMCCH0_0_GeccCtrl__UCFatalEn_MASK                  0x00002000L



#endif