Commit 6de492ae authored by Matt Roper's avatar Matt Roper Committed by Rodrigo Vivi
Browse files

drm/xe/debugfs: Include GFXPIPE commands in LRC dump 



RCS and CCS engines include several non-register gfxpipe commands in
their LRC images.  Include these in the dump output so that we can see
exactly what's inside the context snapshot.

v2:
 - Include raw instruction header in output
 - Add 3DSTATE_AMFS_TEXTURE_POINTERS and 3DSTATE_MONOFILTER_SIZE.  The
   first was supposed to be removed in Xe_HPG, and the second by
   gen12, but both still show up in the RCS LRC.

v3:
 - Sanity check that we don't have numdw > remaining_dw.  (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-14-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 0f60547f

drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h

0 → 100644
+108 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef _XE_GFXPIPE_COMMANDS_H_

#define _XE_GFXPIPE_COMMANDS_H_



#include "instructions/xe_instr_defs.h"



#define GFXPIPE_PIPELINE		REG_GENMASK(28, 27)

#define   PIPELINE_COMMON		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x0)

#define   PIPELINE_SINGLE_DW		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x1)

#define   PIPELINE_COMPUTE		REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x2)

#define   PIPELINE_3D			REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x3)



#define GFXPIPE_OPCODE			REG_GENMASK(26, 24)

#define GFXPIPE_SUBOPCODE		REG_GENMASK(23, 16)



#define GFXPIPE_MATCH_MASK		(XE_INSTR_CMD_TYPE | \

					 GFXPIPE_PIPELINE | \

					 GFXPIPE_OPCODE | \

					 GFXPIPE_SUBOPCODE)



#define GFXPIPE_COMMON_CMD(opcode, subopcode) \

	(XE_INSTR_GFXPIPE | PIPELINE_COMMON | \

	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \

	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))



#define GFXPIPE_SINGLE_DW_CMD(opcode, subopcode) \

	(XE_INSTR_GFXPIPE | PIPELINE_SINGLE_DW | \

	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \

	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))



#define GFXPIPE_3D_CMD(opcode, subopcode) \

	(XE_INSTR_GFXPIPE | PIPELINE_3D | \

	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \

	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))



#define GFXPIPE_COMPUTE_CMD(opcode, subopcode) \

	(XE_INSTR_GFXPIPE | PIPELINE_COMPUTE | \

	 REG_FIELD_PREP(GFXPIPE_OPCODE, opcode) | \

	 REG_FIELD_PREP(GFXPIPE_SUBOPCODE, subopcode))



#define STATE_BASE_ADDRESS			GFXPIPE_COMMON_CMD(0x1, 0x1)

#define STATE_SIP				GFXPIPE_COMMON_CMD(0x1, 0x2)

#define GPGPU_CSR_BASE_ADDRESS			GFXPIPE_COMMON_CMD(0x1, 0x4)

#define STATE_COMPUTE_MODE			GFXPIPE_COMMON_CMD(0x1, 0x5)

#define CMD_3DSTATE_BTD				GFXPIPE_COMMON_CMD(0x1, 0x6)



#define CMD_3DSTATE_VF_STATISTICS		GFXPIPE_SINGLE_DW_CMD(0x0, 0xB)



#define PIPELINE_SELECT				GFXPIPE_SINGLE_DW_CMD(0x1, 0x4)



#define CMD_3DSTATE_CLEAR_PARAMS		GFXPIPE_3D_CMD(0x0, 0x4)

#define CMD_3DSTATE_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x5)

#define CMD_3DSTATE_STENCIL_BUFFER		GFXPIPE_3D_CMD(0x0, 0x6)

#define CMD_3DSTATE_HIER_DEPTH_BUFFER		GFXPIPE_3D_CMD(0x0, 0x7)

#define CMD_3DSTATE_VERTEX_BUFFERS		GFXPIPE_3D_CMD(0x0, 0x8)

#define CMD_3DSTATE_INDEX_BUFFER		GFXPIPE_3D_CMD(0x0, 0xA)

#define CMD_3DSTATE_VF				GFXPIPE_3D_CMD(0x0, 0xC)

#define CMD_3DSTATE_CC_STATE_POINTERS		GFXPIPE_3D_CMD(0x0, 0xE)

#define CMD_3DSTATE_WM				GFXPIPE_3D_CMD(0x0, 0x14)

#define CMD_3DSTATE_SAMPLE_MASK			GFXPIPE_3D_CMD(0x0, 0x18)

#define CMD_3DSTATE_SBE				GFXPIPE_3D_CMD(0x0, 0x1F)

#define CMD_3DSTATE_PS				GFXPIPE_3D_CMD(0x0, 0x20)

#define CMD_3DSTATE_CPS_POINTERS		GFXPIPE_3D_CMD(0x0, 0x22)

#define CMD_3DSTATE_VIEWPORT_STATE_POINTERS_CC	GFXPIPE_3D_CMD(0x0, 0x23)

#define CMD_3DSTATE_BLEND_STATE_POINTERS	GFXPIPE_3D_CMD(0x0, 0x24)

#define CMD_3DSTATE_BINDING_TABLE_POINTERS_PS	GFXPIPE_3D_CMD(0x0, 0x2A)

#define CMD_3DSTATE_SAMPLER_STATE_POINTERS_PS	GFXPIPE_3D_CMD(0x0, 0x2F)

#define CMD_3DSTATE_VF_INSTANCING		GFXPIPE_3D_CMD(0x0, 0x49)

#define CMD_3DSTATE_VF_TOPOLOGY			GFXPIPE_3D_CMD(0x0, 0x4B)

#define CMD_3DSTATE_WM_CHROMAKEY		GFXPIPE_3D_CMD(0x0, 0x4C)

#define CMD_3DSTATE_PS_BLEND			GFXPIPE_3D_CMD(0x0, 0x4D)

#define CMD_3DSTATE_WM_DEPTH_STENCIL		GFXPIPE_3D_CMD(0x0, 0x4E)

#define CMD_3DSTATE_PS_EXTRA			GFXPIPE_3D_CMD(0x0, 0x4F)

#define CMD_3DSTATE_SBE_SWIZ			GFXPIPE_3D_CMD(0x0, 0x51)

#define CMD_3DSTATE_VFG				GFXPIPE_3D_CMD(0x0, 0x57)

#define CMD_3DSTATE_AMFS			GFXPIPE_3D_CMD(0x0, 0x6F)

#define CMD_3DSTATE_DEPTH_BOUNDS		GFXPIPE_3D_CMD(0x0, 0x71)

#define CMD_3DSTATE_AMFS_TEXTURE_POINTERS	GFXPIPE_3D_CMD(0x0, 0x72)

#define CMD_3DSTATE_CONSTANT_TS_POINTER		GFXPIPE_3D_CMD(0x0, 0x73)

#define CMD_3DSTATE_MESH_DISTRIB		GFXPIPE_3D_CMD(0x0, 0x78)

#define CMD_3DSTATE_SBE_MESH			GFXPIPE_3D_CMD(0x0, 0x82)

#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER	GFXPIPE_3D_CMD(0x0, 0x83)



#define CMD_3DSTATE_CHROMA_KEY			GFXPIPE_3D_CMD(0x1, 0x4)

#define CMD_3DSTATE_POLY_STIPPLE_OFFSET		GFXPIPE_3D_CMD(0x1, 0x6)

#define CMD_3DSTATE_POLY_STIPPLE_PATTERN	GFXPIPE_3D_CMD(0x1, 0x7)

#define CMD_3DSTATE_LINE_STIPPLE		GFXPIPE_3D_CMD(0x1, 0x8)

#define CMD_3DSTATE_AA_LINE_PARAMETERS		GFXPIPE_3D_CMD(0x1, 0xA)

#define CMD_3DSTATE_MONOFILTER_SIZE		GFXPIPE_3D_CMD(0x1, 0x11)

#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_VS	GFXPIPE_3D_CMD(0x1, 0x12)

#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_HS	GFXPIPE_3D_CMD(0x1, 0x13)

#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_DS	GFXPIPE_3D_CMD(0x1, 0x14)

#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_GS	GFXPIPE_3D_CMD(0x1, 0x15)

#define CMD_3DSTATE_PUSH_CONSTANT_ALLOC_PS	GFXPIPE_3D_CMD(0x1, 0x16)

#define CMD_3DSTATE_SO_DECL_LIST		GFXPIPE_3D_CMD(0x1, 0x17)

#define   CMD_3DSTATE_SO_DECL_LIST_DW_LEN	REG_GENMASK(8, 0)

#define CMD_3DSTATE_BINDING_TABLE_POOL_ALLOC	GFXPIPE_3D_CMD(0x1, 0x19)

#define CMD_3DSTATE_SAMPLE_PATTERN		GFXPIPE_3D_CMD(0x1, 0x1C)

#define CMD_3DSTATE_3D_MODE			GFXPIPE_3D_CMD(0x1, 0x1E)

#define CMD_3DSTATE_SUBSLICE_HASH_TABLE		GFXPIPE_3D_CMD(0x1, 0x1F)

#define CMD_3DSTATE_SLICE_TABLE_STATE_POINTERS	GFXPIPE_3D_CMD(0x1, 0x20)

#define CMD_3DSTATE_PTBR_TILE_PASS_INFO		GFXPIPE_3D_CMD(0x1, 0x22)



#endif

drivers/gpu/drm/xe/xe_lrc.c

+108 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include "xe_lrc.h"



#include "instructions/xe_mi_commands.h"

#include "instructions/xe_gfxpipe_commands.h"

#include "regs/xe_engine_regs.h"

#include "regs/xe_gpu_commands.h"

#include "regs/xe_gt_regs.h"
@@ -907,6 +908,15 @@ struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc) 


static int instr_dw(u32 cmd_header)

{

	/* GFXPIPE "SINGLE_DW" opcodes are a single dword */

	if ((cmd_header & (XE_INSTR_CMD_TYPE | GFXPIPE_PIPELINE)) ==

	    GFXPIPE_SINGLE_DW_CMD(0, 0))

		return 1;



	/* 3DSTATE_SO_DECL_LIST has a 9-bit dword length rather than 8 */

	if ((cmd_header & GFXPIPE_MATCH_MASK) == CMD_3DSTATE_SO_DECL_LIST)

		return REG_FIELD_GET(CMD_3DSTATE_SO_DECL_LIST_DW_LEN, cmd_header) + 2;



	/* Most instructions have the # of dwords (minus 2) in 7:0 */

	return REG_FIELD_GET(XE_INSTR_LEN_MASK, cmd_header) + 2;

}
@@ -967,6 +977,102 @@ static int dump_mi_command(struct drm_printer *p, 
	}

}



static int dump_gfxpipe_command(struct drm_printer *p,

				struct xe_gt *gt,

				u32 *dw,

				int remaining_dw)

{

	u32 numdw = instr_dw(*dw);

	u32 pipeline = REG_FIELD_GET(GFXPIPE_PIPELINE, *dw);

	u32 opcode = REG_FIELD_GET(GFXPIPE_OPCODE, *dw);

	u32 subopcode = REG_FIELD_GET(GFXPIPE_SUBOPCODE, *dw);



	/*

	 * Make sure we haven't mis-parsed a number of dwords that exceeds the

	 * remaining size of the LRC.

	 */

	if (xe_gt_WARN_ON(gt, numdw > remaining_dw))

		numdw = remaining_dw;



	switch (*dw & GFXPIPE_MATCH_MASK) {

#define MATCH(cmd) \

	case cmd: \

		drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \

		return numdw

#define MATCH3D(cmd) \

	case CMD_##cmd: \

		drm_printf(p, "[%#010x] " #cmd " (%d dwords)\n", *dw, numdw); \

		return numdw



	MATCH(STATE_BASE_ADDRESS);

	MATCH(STATE_SIP);

	MATCH(GPGPU_CSR_BASE_ADDRESS);

	MATCH(STATE_COMPUTE_MODE);

	MATCH3D(3DSTATE_BTD);



	MATCH3D(3DSTATE_VF_STATISTICS);



	MATCH(PIPELINE_SELECT);



	MATCH3D(3DSTATE_CLEAR_PARAMS);

	MATCH3D(3DSTATE_DEPTH_BUFFER);

	MATCH3D(3DSTATE_STENCIL_BUFFER);

	MATCH3D(3DSTATE_HIER_DEPTH_BUFFER);

	MATCH3D(3DSTATE_VERTEX_BUFFERS);

	MATCH3D(3DSTATE_INDEX_BUFFER);

	MATCH3D(3DSTATE_VF);

	MATCH3D(3DSTATE_CC_STATE_POINTERS);

	MATCH3D(3DSTATE_WM);

	MATCH3D(3DSTATE_SAMPLE_MASK);

	MATCH3D(3DSTATE_SBE);

	MATCH3D(3DSTATE_PS);

	MATCH3D(3DSTATE_CPS_POINTERS);

	MATCH3D(3DSTATE_VIEWPORT_STATE_POINTERS_CC);

	MATCH3D(3DSTATE_BLEND_STATE_POINTERS);

	MATCH3D(3DSTATE_BINDING_TABLE_POINTERS_PS);

	MATCH3D(3DSTATE_SAMPLER_STATE_POINTERS_PS);

	MATCH3D(3DSTATE_VF_INSTANCING);

	MATCH3D(3DSTATE_VF_TOPOLOGY);

	MATCH3D(3DSTATE_WM_CHROMAKEY);

	MATCH3D(3DSTATE_PS_BLEND);

	MATCH3D(3DSTATE_WM_DEPTH_STENCIL);

	MATCH3D(3DSTATE_PS_EXTRA);

	MATCH3D(3DSTATE_SBE_SWIZ);

	MATCH3D(3DSTATE_VFG);

	MATCH3D(3DSTATE_AMFS);

	MATCH3D(3DSTATE_DEPTH_BOUNDS);

	MATCH3D(3DSTATE_AMFS_TEXTURE_POINTERS);

	MATCH3D(3DSTATE_CONSTANT_TS_POINTER);

	MATCH3D(3DSTATE_MESH_DISTRIB);

	MATCH3D(3DSTATE_SBE_MESH);

	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);



	MATCH3D(3DSTATE_CHROMA_KEY);

	MATCH3D(3DSTATE_POLY_STIPPLE_OFFSET);

	MATCH3D(3DSTATE_POLY_STIPPLE_PATTERN);

	MATCH3D(3DSTATE_LINE_STIPPLE);

	MATCH3D(3DSTATE_AA_LINE_PARAMETERS);

	MATCH3D(3DSTATE_MONOFILTER_SIZE);

	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_VS);

	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_HS);

	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_DS);

	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_GS);

	MATCH3D(3DSTATE_PUSH_CONSTANT_ALLOC_PS);

	MATCH3D(3DSTATE_SO_DECL_LIST);

	MATCH3D(3DSTATE_BINDING_TABLE_POOL_ALLOC);

	MATCH3D(3DSTATE_SAMPLE_PATTERN);

	MATCH3D(3DSTATE_3D_MODE);

	MATCH3D(3DSTATE_SUBSLICE_HASH_TABLE);

	MATCH3D(3DSTATE_SLICE_TABLE_STATE_POINTERS);

	MATCH3D(3DSTATE_PTBR_TILE_PASS_INFO);



	default:

		drm_printf(p, "[%#010x] unknown GFXPIPE command (pipeline=%#x, opcode=%#x, subopcode=%#x), likely %d dwords\n",

			   *dw, pipeline, opcode, subopcode, numdw);

		return numdw;

	}

}



void xe_lrc_dump_default(struct drm_printer *p,

			 struct xe_gt *gt,

			 enum xe_engine_class hwe_class)
@@ -989,6 +1095,8 @@ void xe_lrc_dump_default(struct drm_printer *p, 
	while (remaining_dw > 0) {

		if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_MI) {

			num_dw = dump_mi_command(p, gt, dw, remaining_dw);

		} else if ((*dw & XE_INSTR_CMD_TYPE) == XE_INSTR_GFXPIPE) {

			num_dw = dump_gfxpipe_command(p, gt, dw, remaining_dw);

		} else {

			num_dw = min(instr_dw(*dw), remaining_dw);

			drm_printf(p, "[%#10x] Unknown instruction of type %#x, likely %d dwords\n",