Commit 6e3cb25e authored by Akhil R's avatar Akhil R Committed by Wolfram Sang
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i2c: tegra: Add Tegra256 support 



Add compatible and the hardware struct for Tegra256. Tegra256 controllers
use a different parent clock. Hence the timing parameters are different
from the previous generations to meet the expected frequencies.

Signed-off-by: default avatarAkhil R <akhilrajeev@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
parent 69329daf

drivers/i2c/busses/i2c-tegra.c

+26 −0
Original line number Diff line number Diff line
@@ -1649,7 +1649,33 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 
	.has_interface_timing_reg = true,

};



static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {

	.has_continue_xfer_support = true,

	.has_per_pkt_xfer_complete_irq = true,

	.clk_divisor_hs_mode = 7,

	.clk_divisor_std_mode = 0x7a,

	.clk_divisor_fast_mode = 0x40,

	.clk_divisor_fast_plus_mode = 0x19,

	.has_config_load_reg = true,

	.has_multi_master_mode = true,

	.has_slcg_override_reg = true,

	.has_mst_fifo = true,

	.has_mst_reset = true,

	.quirks = &tegra194_i2c_quirks,

	.supports_bus_clear = true,

	.has_apb_dma = false,

	.tlow_std_mode = 0x8,

	.thigh_std_mode = 0x7,

	.tlow_fast_fastplus_mode = 0x3,

	.thigh_fast_fastplus_mode = 0x3,

	.setup_hold_time_std_mode = 0x08080808,

	.setup_hold_time_fast_fast_plus_mode = 0x02020202,

	.setup_hold_time_hs_mode = 0x090909,

	.has_interface_timing_reg = true,

};



static const struct of_device_id tegra_i2c_of_match[] = {

	{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },

	{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },

	{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },

#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)