Commit 6e51b4b5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:
 "Just cleanups and fixes"

* tag 'mips_6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (24 commits)
  MIPS: Take in account load hazards for HI/LO restoring
  MIPS: SGI-IP27: use WARN_ON() output
  MIPS: SGI-IP27: fix -Wunused-variable in arch_init_irq()
  MIPS: SGI-IP27: micro-optimize arch_init_irq()
  mips: dts: ralink: mt7621: reorder the attributes of the root node
  mips: dts: ralink: mt7621: reorder pci?_phy attributes
  mips: dts: ralink: mt7621: reorder pcie node attributes and children
  mips: dts: ralink: mt7621: reorder ethernet node attributes and kids
  mips: dts: ralink: mt7621: reorder gic node attributes
  mips: dts: ralink: mt7621: reorder mmc node attributes
  mips: dts: ralink: mt7621: move pinctrl and sort its children
  mips: dts: ralink: mt7621: reorder spi0 node attributes
  mips: dts: ralink: mt7621: reorder i2c node attributes
  mips: dts: ralink: mt7621: reorder gpio node attributes
  mips: dts: ralink: mt7621: reorder sysc node attributes
  mips: dts: ralink: mt7621: reorder mmc regulator attributes
  mips: dts: ralink: mt7621: reorder cpuintc node attributes
  mips: dts: ralink: mt7621: reorder cpu node attributes
  MIPS: Add prototypes for plat_post_relocation() and relocate_kernel()
  MIPS: Octeon: Add PCIe link status check
  ...
parents 80f9d902 07e6a6d7

arch/mips/bcm47xx/prom.c

+2 −1
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include <asm/bootinfo.h>

#include <bcm47xx.h>

#include <bcm47xx_board.h>

#include "bcm47xx_private.h"



static char bcm47xx_system_type[20] = "Broadcom BCM47XX";
@@ -123,7 +124,7 @@ void __init prom_init(void) 
/* Stripped version of tlb_init, with the call to build_tlb_refill_handler

 * dropped. Calling it at this stage causes a hang.

 */

void early_tlb_init(void)

static void early_tlb_init(void)

{

	write_c0_pagemask(PM_DEFAULT_MASK);

	write_c0_wired(0);

arch/mips/boot/dts/ralink/mt7621.dtsi

+239 −191
Original line number Diff line number Diff line
@@ -5,50 +5,143 @@ 
#include <dt-bindings/reset/mt7621-reset.h>



/ {

	compatible = "mediatek,mt7621-soc";



	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "mediatek,mt7621-soc";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "mips,mips1004Kc";

			reg = <0>;

			device_type = "cpu";

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "mips,mips1004Kc";

			reg = <1>;

			device_type = "cpu";

		};

	};



	cpuintc: cpuintc {

		compatible = "mti,cpu-interrupt-controller";



		#address-cells = <0>;

		#interrupt-cells = <1>;



		interrupt-controller;

		compatible = "mti,cpu-interrupt-controller";

	};



	mmc_fixed_3v3: regulator-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "mmc_power";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		enable-active-high;



		regulator-always-on;

		regulator-max-microvolt = <3300000>;

		regulator-min-microvolt = <3300000>;

		regulator-name = "mmc_power";

	};



	mmc_fixed_1v8_io: regulator-1v8 {

		compatible = "regulator-fixed";

		regulator-name = "mmc_io";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;



		enable-active-high;



		regulator-always-on;

		regulator-max-microvolt = <1800000>;

		regulator-min-microvolt = <1800000>;

		regulator-name = "mmc_io";

	};



	pinctrl: pinctrl {

		compatible = "ralink,mt7621-pinctrl";



		i2c_pins: i2c0-pins {

			pinmux {

				groups = "i2c";

				function = "i2c";

			};

		};



		mdio_pins: mdio0-pins {

			pinmux {

				groups = "mdio";

				function = "mdio";

			};

		};



		nand_pins: nand0-pins {

			sdhci-pinmux {

				groups = "sdhci";

				function = "nand2";

			};



			spi-pinmux {

				groups = "spi";

				function = "nand1";

			};

		};



		pcie_pins: pcie0-pins {

			pinmux {

				groups = "pcie";

				function = "gpio";

			};

		};



		rgmii1_pins: rgmii1-pins {

			pinmux {

				groups = "rgmii1";

				function = "rgmii1";

			};

		};



		rgmii2_pins: rgmii2-pins {

			pinmux {

				groups = "rgmii2";

				function = "rgmii2";

			};

		};



		sdhci_pins: sdhci0-pins {

			pinmux {

				groups = "sdhci";

				function = "sdhci";

			};

		};



		spi_pins: spi0-pins {

			pinmux {

				groups = "spi";

				function = "spi";

			};

		};



		uart1_pins: uart1-pins {

			pinmux {

				groups = "uart1";

				function = "uart1";

			};

		};



		uart2_pins: uart2-pins {

			pinmux {

				groups = "uart2";

				function = "uart2";

			};

		};



		uart3_pins: uart3-pins {

			pinmux {

				groups = "uart3";

				function = "uart3";

			};

		};

	};



	palmbus: palmbus@1e000000 {
@@ -62,12 +155,15 @@ palmbus: palmbus@1e000000 { 
		sysc: syscon@0 {

			compatible = "mediatek,mt7621-sysc", "syscon";

			reg = <0x0 0x100>;



			#clock-cells = <1>;

			#reset-cells = <1>;

			ralink,memctl = <&memc>;



			clock-output-names = "xtal", "cpu", "bus",

					     "50m", "125m", "150m",

					     "250m", "270m";



			ralink,memctl = <&memc>;

		};



		wdt: watchdog@100 {
@@ -77,13 +173,16 @@ wdt: watchdog@100 { 
		};



		gpio: gpio@600 {

			compatible = "mediatek,mt7621-gpio";

			reg = <0x600 0x100>;



			#gpio-cells = <2>;

			#interrupt-cells = <2>;

			compatible = "mediatek,mt7621-gpio";



			gpio-controller;

			gpio-ranges = <&pinctrl 0 0 95>;



			interrupt-controller;

			reg = <0x600 0x100>;

			interrupt-parent = <&gic>;

			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;

		};
@@ -92,18 +191,19 @@ i2c: i2c@900 { 
			compatible = "mediatek,mt7621-i2c";

			reg = <0x900 0x100>;



			clocks = <&sysc MT7621_CLK_I2C>;

			clock-names = "i2c";

			resets = <&sysc MT7621_RST_I2C>;

			reset-names = "i2c";



			#address-cells = <1>;

			#size-cells = <0>;



			status = "disabled";

			clocks = <&sysc MT7621_CLK_I2C>;

			clock-names = "i2c";



			pinctrl-names = "default";

			pinctrl-0 = <&i2c_pins>;



			resets = <&sysc MT7621_RST_I2C>;

			reset-names = "i2c";



			status = "disabled";

		};



		memc: memory-controller@5000 {
@@ -170,135 +270,53 @@ serial2: serial@e00 { 
		};



		spi0: spi@b00 {

			status = "disabled";



			compatible = "ralink,mt7621-spi";

			reg = <0xb00 0x100>;



			clocks = <&sysc MT7621_CLK_SPI>;

			clock-names = "spi";



			resets = <&sysc MT7621_RST_SPI>;

			reset-names = "spi";



			#address-cells = <1>;

			#size-cells = <0>;



			clock-names = "spi";

			clocks = <&sysc MT7621_CLK_SPI>;



			pinctrl-names = "default";

			pinctrl-0 = <&spi_pins>;

		};

	};



	pinctrl: pinctrl {

		compatible = "ralink,mt7621-pinctrl";



		i2c_pins: i2c0-pins {

			pinmux {

				groups = "i2c";

				function = "i2c";

			};

		};



		spi_pins: spi0-pins {

			pinmux {

				groups = "spi";

				function = "spi";

			};

		};



		uart1_pins: uart1-pins {

			pinmux {

				groups = "uart1";

				function = "uart1";

			};

		};



		uart2_pins: uart2-pins {

			pinmux {

				groups = "uart2";

				function = "uart2";

			};

		};



		uart3_pins: uart3-pins {

			pinmux {

				groups = "uart3";

				function = "uart3";

			};

		};



		rgmii1_pins: rgmii1-pins {

			pinmux {

				groups = "rgmii1";

				function = "rgmii1";

			};

		};



		rgmii2_pins: rgmii2-pins {

			pinmux {

				groups = "rgmii2";

				function = "rgmii2";

			};

		};



		mdio_pins: mdio0-pins {

			pinmux {

				groups = "mdio";

				function = "mdio";

			};

		};



		pcie_pins: pcie0-pins {

			pinmux {

				groups = "pcie";

				function = "gpio";

			};

		};



		nand_pins: nand0-pins {

			spi-pinmux {

				groups = "spi";

				function = "nand1";

			};



			sdhci-pinmux {

				groups = "sdhci";

				function = "nand2";

			};

		};

			reset-names = "spi";

			resets = <&sysc MT7621_RST_SPI>;



		sdhci_pins: sdhci0-pins {

			pinmux {

				groups = "sdhci";

				function = "sdhci";

			};

			status = "disabled";

		};

	};



	mmc: mmc@1e130000 {

		status = "disabled";



		compatible = "mediatek,mt7620-mmc";

		reg = <0x1e130000 0x4000>;



		bus-width = <4>;

		max-frequency = <48000000>;

		cap-sd-highspeed;

		cap-mmc-highspeed;

		vmmc-supply = <&mmc_fixed_3v3>;

		vqmmc-supply = <&mmc_fixed_1v8_io>;

		disable-wp;



		pinctrl-names = "default", "state_uhs";

		pinctrl-0 = <&sdhci_pins>;

		pinctrl-1 = <&sdhci_pins>;

		cap-mmc-highspeed;

		cap-sd-highspeed;



		clocks = <&sysc MT7621_CLK_SHXC>,

			 <&sysc MT7621_CLK_50M>;

		clock-names = "source", "hclk";



		disable-wp;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;



		max-frequency = <48000000>;



		pinctrl-names = "default", "state_uhs";

		pinctrl-0 = <&sdhci_pins>;

		pinctrl-1 = <&sdhci_pins>;



		vmmc-supply = <&mmc_fixed_3v3>;

		vqmmc-supply = <&mmc_fixed_1v8_io>;



		status = "disabled";

	};



	usb: usb@1e1c0000 {
@@ -321,15 +339,15 @@ gic: interrupt-controller@1fbc0000 { 
		compatible = "mti,gic";

		reg = <0x1fbc0000 0x2000>;



		interrupt-controller;

		#interrupt-cells = <3>;

		interrupt-controller;



		mti,reserved-cpu-vectors = <7>;



		timer {

			compatible = "mti,gic-timer";

			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

			clocks = <&sysc MT7621_CLK_CPU>;

			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;

		};

	};
@@ -347,46 +365,22 @@ ethernet: ethernet@1e100000 { 
		compatible = "mediatek,mt7621-eth";

		reg = <0x1e100000 0x10000>;



		clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;

		clock-names = "fe", "ethif";



		#address-cells = <1>;

		#size-cells = <0>;



		resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;

		reset-names = "fe", "eth";

		clock-names = "fe", "ethif";

		clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;



		interrupt-parent = <&gic>;

		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;



		mediatek,ethsys = <&sysc>;



		pinctrl-names = "default";

		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;



		gmac0: mac@0 {

			compatible = "mediatek,eth-mac";

			reg = <0>;

			phy-mode = "trgmii";



			fixed-link {

				speed = <1000>;

				full-duplex;

				pause;

			};

		};



		gmac1: mac@1 {

			compatible = "mediatek,eth-mac";

			reg = <1>;

			phy-mode = "rgmii";

		reset-names = "fe", "eth";

		resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;



			fixed-link {

				speed = <1000>;

				full-duplex;

				pause;

			};

		};

		mediatek,ethsys = <&sysc>;



		mdio: mdio-bus {

			#address-cells = <1>;
@@ -395,73 +389,105 @@ mdio: mdio-bus { 
			switch0: switch@1f {

				compatible = "mediatek,mt7621";

				reg = <0x1f>;

				mediatek,mcm;

				resets = <&sysc MT7621_RST_MCM>;

				reset-names = "mcm";

				interrupt-controller;



				#interrupt-cells = <1>;

				interrupt-controller;

				interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;



				reset-names = "mcm";

				resets = <&sysc MT7621_RST_MCM>;



				mediatek,mcm;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						status = "disabled";

						reg = <0>;

						label = "swp0";

						status = "disabled";

					};



					port@1 {

						status = "disabled";

						reg = <1>;

						label = "swp1";

						status = "disabled";

					};



					port@2 {

						status = "disabled";

						reg = <2>;

						label = "swp2";

						status = "disabled";

					};



					port@3 {

						status = "disabled";

						reg = <3>;

						label = "swp3";

						status = "disabled";

					};



					port@4 {

						status = "disabled";

						reg = <4>;

						label = "swp4";

						status = "disabled";

					};



					port@5 {

						reg = <5>;



						ethernet = <&gmac1>;

						phy-mode = "rgmii";



						fixed-link {

							speed = <1000>;

							full-duplex;

							pause;

							speed = <1000>;

						};

					};



					port@6 {

						reg = <6>;



						ethernet = <&gmac0>;

						phy-mode = "trgmii";



						fixed-link {

							speed = <1000>;

							full-duplex;

							pause;

							speed = <1000>;

						};

					};

				};

			};

		};



		gmac0: mac@0 {

			compatible = "mediatek,eth-mac";

			reg = <0>;



			phy-mode = "trgmii";



			fixed-link {

				full-duplex;

				pause;

				speed = <1000>;

			};

		};



		gmac1: mac@1 {

			compatible = "mediatek,eth-mac";

			reg = <1>;



			phy-mode = "rgmii";



			fixed-link {

				full-duplex;

				pause;

				speed = <1000>;

			};

		};



	};



	pcie: pcie@1e140000 {
@@ -470,84 +496,106 @@ pcie: pcie@1e140000 { 
		      <0x1e142000 0x100>, /* pcie port 0 RC control registers */

		      <0x1e143000 0x100>, /* pcie port 1 RC control registers */

		      <0x1e144000 0x100>; /* pcie port 2 RC control registers */

		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */

			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */



		#address-cells = <3>;

		#interrupt-cells = <1>;

		#size-cells = <2>;



		pinctrl-names = "default";

		pinctrl-0 = <&pcie_pins>;



		device_type = "pci";



		ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */

			 <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */



		#interrupt-cells = <1>;

		interrupt-map-mask = <0xF800 0 0 0>;

		interrupt-map-mask = <0xf800 0 0 0>;

		interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED  4 IRQ_TYPE_LEVEL_HIGH>,

				<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,

				<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;



		status = "disabled";

		pinctrl-names = "default";

		pinctrl-0 = <&pcie_pins>;



		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;



		status = "disabled";



		pcie@0,0 {

			reg = <0x0000 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE0>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE0>;

			clocks = <&sysc MT7621_CLK_PCIE0>;

			phys = <&pcie0_phy 1>;



			phy-names = "pcie-phy0";

			ranges;

			phys = <&pcie0_phy 1>;



			resets = <&sysc MT7621_RST_PCIE0>;

		};



		pcie@1,0 {

			reg = <0x0800 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE1>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE1>;

			clocks = <&sysc MT7621_CLK_PCIE1>;

			phys = <&pcie0_phy 1>;



			phy-names = "pcie-phy1";

			ranges;

			phys = <&pcie0_phy 1>;



			resets = <&sysc MT7621_RST_PCIE1>;

		};



		pcie@2,0 {

			reg = <0x1000 0 0 0 0>;

			ranges;



			#address-cells = <3>;

			#interrupt-cells = <1>;

			#size-cells = <2>;



			clocks = <&sysc MT7621_CLK_PCIE2>;



			device_type = "pci";

			#interrupt-cells = <1>;



			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&sysc MT7621_RST_PCIE2>;

			clocks = <&sysc MT7621_CLK_PCIE2>;

			phys = <&pcie2_phy 0>;



			phy-names = "pcie-phy2";

			ranges;

			phys = <&pcie2_phy 0>;



			resets = <&sysc MT7621_RST_PCIE2>;

		};

	};



	pcie0_phy: pcie-phy@1e149000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e149000 0x0700>;

		clocks = <&sysc MT7621_CLK_XTAL>;



		#phy-cells = <1>;



		clocks = <&sysc MT7621_CLK_XTAL>;

	};



	pcie2_phy: pcie-phy@1e14a000 {

		compatible = "mediatek,mt7621-pci-phy";

		reg = <0x1e14a000 0x0700>;

		clocks = <&sysc MT7621_CLK_XTAL>;



		#phy-cells = <1>;



		clocks = <&sysc MT7621_CLK_XTAL>;

	};

};

arch/mips/include/asm/asm.h

+3 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define CFI_SECTIONS

#endif



#ifdef __ASSEMBLY__

/*

 * LEAF - declare leaf routine

 */
@@ -122,6 +123,8 @@ symbol = value 
#define ASM_PRINT(string)

#endif



#endif /* __ASSEMBLY__ */



/*

 * Stack alignment

 */

arch/mips/include/asm/setup.h

+6 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#ifndef _MIPS_SETUP_H

#define _MIPS_SETUP_H



#include <linux/init.h>

#include <linux/types.h>

#include <uapi/asm/setup.h>
@@ -29,4 +30,9 @@ extern void per_cpu_trap_init(bool); 
extern void cpu_cache_init(void);

extern void tlb_init(void);



#ifdef CONFIG_RELOCATABLE

extern void * __init relocate_kernel(void);

extern int plat_post_relocation(long);

#endif



#endif /* __SETUP_H */

arch/mips/include/asm/stackframe.h

+11 −8
Original line number Diff line number Diff line
@@ -308,17 +308,12 @@ 
		jal	octeon_mult_restore

#endif

#ifdef CONFIG_CPU_HAS_SMARTMIPS

		LONG_L	$24, PT_ACX(sp)

		mtlhx	$24

		LONG_L	$24, PT_HI(sp)

		mtlhx	$24

		LONG_L	$14, PT_ACX(sp)

		LONG_L	$24, PT_LO(sp)

		mtlhx	$24

		LONG_L	$15, PT_HI(sp)

#elif !defined(CONFIG_CPU_MIPSR6)

		LONG_L	$24, PT_LO(sp)

		mtlo	$24

		LONG_L	$24, PT_HI(sp)

		mthi	$24

		LONG_L	$15, PT_HI(sp)

#endif

#ifdef CONFIG_32BIT

		cfi_ld	$8, PT_R8, \docfi
@@ -327,6 +322,14 @@ 
		cfi_ld	$10, PT_R10, \docfi

		cfi_ld	$11, PT_R11, \docfi

		cfi_ld	$12, PT_R12, \docfi

#ifdef CONFIG_CPU_HAS_SMARTMIPS

		mtlhx	$14

		mtlhx	$15

		mtlhx	$24

#elif !defined(CONFIG_CPU_MIPSR6)

		mtlo	$24

		mthi	$15

#endif

		cfi_ld	$13, PT_R13, \docfi

		cfi_ld	$14, PT_R14, \docfi

		cfi_ld	$15, PT_R15, \docfi