Loading arch/sparc64/kernel/traps.c +15 −3 Original line number Diff line number Diff line Loading @@ -2261,8 +2261,12 @@ void die_if_kernel(char *str, struct pt_regs *regs) do_exit(SIGSEGV); } #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) extern int handle_popc(u32 insn, struct pt_regs *regs); extern int handle_ldf_stq(u32 insn, struct pt_regs *regs); extern int vis_emul(struct pt_regs *, unsigned int); void do_illegal_instruction(struct pt_regs *regs) { Loading @@ -2287,10 +2291,18 @@ void do_illegal_instruction(struct pt_regs *regs) if (handle_ldf_stq(insn, regs)) return; } else if (tlb_type == hypervisor) { extern int vis_emul(struct pt_regs *, unsigned int); if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) { if (!vis_emul(regs, insn)) return; } else { struct fpustate *f = FPUSTATE; /* XXX maybe verify XFSR bits like * XXX do_fpother() does? */ if (do_mathemu(regs, f)) return; } } } info.si_signo = SIGILL; Loading arch/sparc64/kernel/visemul.c +0 −6 Original line number Diff line number Diff line Loading @@ -128,9 +128,6 @@ /* 001001100 - Permute bytes as specified by GSR.MASK */ #define BSHUFFLE_OPF 0x04c #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) #define VIS_OPF_SHIFT 5 #define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT) Loading Loading @@ -810,9 +807,6 @@ int vis_emul(struct pt_regs *regs, unsigned int insn) if (get_user(insn, (u32 __user *) pc)) return -EFAULT; if ((insn & VIS_OPCODE_MASK) != VIS_OPCODE_VAL) return -EINVAL; opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT; switch (opf) { default: Loading Loading
arch/sparc64/kernel/traps.c +15 −3 Original line number Diff line number Diff line Loading @@ -2261,8 +2261,12 @@ void die_if_kernel(char *str, struct pt_regs *regs) do_exit(SIGSEGV); } #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) extern int handle_popc(u32 insn, struct pt_regs *regs); extern int handle_ldf_stq(u32 insn, struct pt_regs *regs); extern int vis_emul(struct pt_regs *, unsigned int); void do_illegal_instruction(struct pt_regs *regs) { Loading @@ -2287,10 +2291,18 @@ void do_illegal_instruction(struct pt_regs *regs) if (handle_ldf_stq(insn, regs)) return; } else if (tlb_type == hypervisor) { extern int vis_emul(struct pt_regs *, unsigned int); if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) { if (!vis_emul(regs, insn)) return; } else { struct fpustate *f = FPUSTATE; /* XXX maybe verify XFSR bits like * XXX do_fpother() does? */ if (do_mathemu(regs, f)) return; } } } info.si_signo = SIGILL; Loading
arch/sparc64/kernel/visemul.c +0 −6 Original line number Diff line number Diff line Loading @@ -128,9 +128,6 @@ /* 001001100 - Permute bytes as specified by GSR.MASK */ #define BSHUFFLE_OPF 0x04c #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19)) #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19)) #define VIS_OPF_SHIFT 5 #define VIS_OPF_MASK (0x1ff << VIS_OPF_SHIFT) Loading Loading @@ -810,9 +807,6 @@ int vis_emul(struct pt_regs *regs, unsigned int insn) if (get_user(insn, (u32 __user *) pc)) return -EFAULT; if ((insn & VIS_OPCODE_MASK) != VIS_OPCODE_VAL) return -EINVAL; opf = (insn & VIS_OPF_MASK) >> VIS_OPF_SHIFT; switch (opf) { default: Loading