Commit 6e7c4cc5 authored by Sibi Sankar's avatar Sibi Sankar Committed by Jassi Brar
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dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings 



Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
controller.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: default avatarJassi Brar <jassisinghbrar@gmail.com>
parent af5da7b0

Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml

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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller



maintainers:

  - Sibi Sankar <quic_sibis@quicinc.com>



description:

  The CPUSS Control Processor (CPUCP) mailbox controller enables communication

  between AP and CPUCP by acting as a doorbell between them.



properties:

  compatible:

    items:

      - const: qcom,x1e80100-cpucp-mbox



  reg:

    items:

      - description: CPUCP rx register region

      - description: CPUCP tx register region



  interrupts:

    maxItems: 1



  "#mbox-cells":

    const: 1



required:

  - compatible

  - reg

  - interrupts

  - "#mbox-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    mailbox@17430000 {

        compatible = "qcom,x1e80100-cpucp-mbox";

        reg = <0x17430000 0x10000>, <0x18830000 0x10000>;

        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

        #mbox-cells = <1>;

    };