Commit 6ed08741 authored by Haibo Chen's avatar Haibo Chen Committed by Shawn Guo
Browse files

arm64: dts: imx95: add flexcan[1..5] support 



Add the flexcan[1..5] nodes for imx95.

Reviewed-by: default avatarHan Xu <han.xu@nxp.com>
Signed-off-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent abfd53a7

arch/arm64/boot/dts/freescale/imx95.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -713,6 +713,34 @@ lpuart6: serial@425a0000 { 
				status = "disabled";

			};



			flexcan2: can@425b0000 {

				compatible = "fsl,imx95-flexcan";

				reg = <0x425b0000 0x10000>;

				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,

					 <&scmi_clk IMX95_CLK_CAN2>;

				clock-names = "ipg", "per";

				assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>;

				assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

				assigned-clock-rates = <40000000>;

				fsl,clk-source = /bits/ 8 <0>;

				status = "disabled";

			};



			flexcan3: can@42600000 {

				compatible = "fsl,imx95-flexcan";

				reg = <0x42600000 0x10000>;

				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,

					 <&scmi_clk IMX95_CLK_CAN3>;

				clock-names = "ipg", "per";

				assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>;

				assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

				assigned-clock-rates = <40000000>;

				fsl,clk-source = /bits/ 8 <0>;

				status = "disabled";

			};



			flexspi1: spi@425e0000 {

				compatible = "nxp,imx8mm-fspi";

				reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>;
@@ -931,6 +959,34 @@ mu8: mailbox@42730000 { 
				#mbox-cells = <2>;

				status = "disabled";

			};



			flexcan4: can@427c0000 {

				compatible = "fsl,imx95-flexcan";

				reg = <0x427c0000 0x10000>;

				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,

					 <&scmi_clk IMX95_CLK_CAN4>;

				clock-names = "ipg", "per";

				assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>;

				assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

				assigned-clock-rates = <40000000>;

				fsl,clk-source = /bits/ 8 <0>;

				status = "disabled";

			};



			flexcan5: can@427d0000 {

				compatible = "fsl,imx95-flexcan";

				reg = <0x427d0000 0x10000>;

				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,

					 <&scmi_clk IMX95_CLK_CAN5>;

				clock-names = "ipg", "per";

				assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>;

				assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

				assigned-clock-rates = <40000000>;

				fsl,clk-source = /bits/ 8 <0>;

				status = "disabled";

			};

		};



		aips3: bus@42800000 {
@@ -1205,6 +1261,20 @@ lpuart2: serial@44390000 { 
				status = "disabled";

			};



			flexcan1: can@443a0000 {

				compatible = "fsl,imx95-flexcan";

				reg = <0x443a0000 0x10000>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&scmi_clk IMX95_CLK_BUSAON>,

					 <&scmi_clk IMX95_CLK_CAN1>;

				clock-names = "ipg", "per";

				assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>;

				assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;

				assigned-clock-rates = <40000000>;

				fsl,clk-source = /bits/ 8 <0>;

				status = "disabled";

			};



			sai1: sai@443b0000 {

				compatible = "fsl,imx95-sai";

				reg = <0x443b0000 0x10000>;