Commit 6f15b178 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Borislav Petkov (AMD)
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EDAC/versal: Add a Xilinx Versal memory controller driver 

Add a EDAC driver for the RAS capabilities on the Xilinx integrated DDR
Memory Controllers (DDRMCs) which support both DDR4 and LPDDR4/4X memory
interfaces. It has four programmable Network-on-Chip (NoC) interface
ports and is designed to handle multiple streams of traffic. The driver
reports correctable and uncorrectable errors, and also creates debugfs
entries for testing through error injection.

  [ bp:
   - Add a pointer to the documentation about the register unlock code.
   - Squash in a fix for a Smatch static checker issue as reported by
     Dan Carpenter:
     https://lore.kernel.org/r/a4db6f93-8e5f-4d55-a7b8-b5a987d48a58@moroto.mountain


  ]

Co-developed-by: default avatarSai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: default avatarSai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20231005101242.14621-3-shubhrajyoti.datta@amd.com
parent 82bcca7b

MAINTAINERS

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@@ -23719,6 +23719,13 @@ F: Documentation/devicetree/bindings/media/xilinx/ 
F:	drivers/media/platform/xilinx/

F:	include/uapi/linux/xilinx-v4l2-controls.h









XILINX VERSAL EDAC DRIVER









M:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>









M:	Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>









S:	Maintained









F:	Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml









F:	drivers/edac/versal_edac.c

















XILINX WATCHDOG DRIVER









M:	Srinivas Neeli <srinivas.neeli@amd.com>









R:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

























drivers/edac/Kconfig



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@@ -561,4 +561,16 @@ config EDAC_NPCM







	  error detection (in-line ECC in which a section 1/8th of the memory









	  device used to store data is used for ECC storage).



















config EDAC_VERSAL









	tristate "Xilinx Versal DDR Memory Controller"









	depends on ARCH_ZYNQMP || COMPILE_TEST









	help









	  Support for error detection and correction on the Xilinx Versal DDR









	  memory controller.



















	  Report both single bit errors (CE) and double bit errors (UE).









	  Support injecting both correctable and uncorrectable errors









	  for debugging purposes.





























endif # EDAC
























drivers/edac/Makefile



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@@ -86,3 +86,4 @@ obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o







obj-$(CONFIG_EDAC_DMC520)		+= dmc520_edac.o









obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o









obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o









obj-$(CONFIG_EDAC_VERSAL)		+= versal_edac.o
























drivers/edac/versal_edac.c
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include/linux/firmware/xlnx-zynqmp.h



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@@ -100,6 +100,18 @@







#define SD_ITAPDLY	0xFF180314









#define SD_OTAPDLYSEL	0xFF180318



















/**









 * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error.









 */









#define XPM_EVENT_ERROR_MASK_DDRMC_CR		BIT(18)



















/**









 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.









 */









#define XPM_EVENT_ERROR_MASK_DDRMC_NCR		BIT(19)









#define XPM_EVENT_ERROR_MASK_NOC_NCR		BIT(13)









#define XPM_EVENT_ERROR_MASK_NOC_CR		BIT(12)



















enum pm_api_cb_id {









	PM_INIT_SUSPEND_CB = 30,









	PM_ACKNOWLEDGE_CB = 31,