Commit 6f34024d authored by Oliver Upton's avatar Oliver Upton
Browse files

KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3 



KVM is about to learn some new tricks to virtualize PMUv3 on IMPDEF
hardware. As part of that, we now need to differentiate host support
from guest support for PMUv3.

Add a cpucap to determine if an architectural PMUv3 is present to guard
host usage of PMUv3 controls.

Tested-by: default avatarJanne Grunau <j@jannau.net>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250305202641.428114-6-oliver.upton@linux.dev


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent ed335722

arch/arm64/include/asm/cpucaps.h

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ cpucap_is_possible(const unsigned int cap) 
		 * KVM MPAM support doesn't rely on the host kernel supporting MPAM.

		*/

		return true;

	case ARM64_HAS_PMUV3:

		return IS_ENABLED(CONFIG_HW_PERF_EVENTS);

	}



	return true;

arch/arm64/include/asm/cpufeature.h

+5 −0
Original line number Diff line number Diff line
@@ -866,6 +866,11 @@ static __always_inline bool system_supports_mpam_hcr(void) 
	return alternative_has_cap_unlikely(ARM64_MPAM_HCR);

}



static inline bool system_supports_pmuv3(void)

{

	return cpus_have_final_cap(ARM64_HAS_PMUV3);

}



int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);

bool try_emulate_mrs(struct pt_regs *regs, u32 isn);

arch/arm64/kernel/cpufeature.c

+30 −0
Original line number Diff line number Diff line
@@ -1898,6 +1898,28 @@ static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 
}

#endif



#ifdef CONFIG_HW_PERF_EVENTS

static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope)

{

	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);

	unsigned int pmuver;



	/*

	 * PMUVer follows the standard ID scheme for an unsigned field with the

	 * exception of 0xF (IMP_DEF) which is treated specially and implies

	 * FEAT_PMUv3 is not implemented.

	 *

	 * See DDI0487L.a D24.1.3.2 for more details.

	 */

	pmuver = cpuid_feature_extract_unsigned_field(dfr0,

						      ID_AA64DFR0_EL1_PMUVer_SHIFT);

	if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)

		return false;



	return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP;

}

#endif



#ifdef CONFIG_UNMAP_KERNEL_AT_EL0

#define KPTI_NG_TEMP_VA		(-(1UL << PMD_SHIFT))
@@ -2998,6 +3020,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP)

	},

#endif

#ifdef CONFIG_HW_PERF_EVENTS

	{

		.desc = "PMUv3",

		.capability = ARM64_HAS_PMUV3,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_pmuv3,

	},

#endif

	{},

};

arch/arm64/kvm/hyp/include/hyp/switch.h

+2 −2
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) 
	 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at

	 * EL1 instead of being trapped to EL2.

	 */

	if (kvm_arm_support_pmu_v3()) {

	if (system_supports_pmuv3()) {

		struct kvm_cpu_context *hctxt;



		write_sysreg(0, pmselr_el0);
@@ -281,7 +281,7 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) 
	write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2);



	write_sysreg(0, hstr_el2);

	if (kvm_arm_support_pmu_v3()) {

	if (system_supports_pmuv3()) {

		struct kvm_cpu_context *hctxt;



		hctxt = host_data_ptr(host_ctxt);

arch/arm64/kvm/pmu.c

+5 −5
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) 
{

	struct kvm_pmu_events *pmu = kvm_get_pmu_events();



	if (!kvm_arm_support_pmu_v3() || !kvm_pmu_switch_needed(attr))

	if (!system_supports_pmuv3() || !kvm_pmu_switch_needed(attr))

		return;



	if (!attr->exclude_host)
@@ -57,7 +57,7 @@ void kvm_clr_pmu_events(u64 clr) 
{

	struct kvm_pmu_events *pmu = kvm_get_pmu_events();



	if (!kvm_arm_support_pmu_v3())

	if (!system_supports_pmuv3())

		return;



	pmu->events_host &= ~clr;
@@ -133,7 +133,7 @@ void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) 
	struct kvm_pmu_events *pmu;

	u64 events_guest, events_host;



	if (!kvm_arm_support_pmu_v3() || !has_vhe())

	if (!system_supports_pmuv3() || !has_vhe())

		return;



	preempt_disable();
@@ -154,7 +154,7 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) 
	struct kvm_pmu_events *pmu;

	u64 events_guest, events_host;



	if (!kvm_arm_support_pmu_v3() || !has_vhe())

	if (!system_supports_pmuv3() || !has_vhe())

		return;



	pmu = kvm_get_pmu_events();
@@ -180,7 +180,7 @@ bool kvm_set_pmuserenr(u64 val) 
	struct kvm_cpu_context *hctxt;

	struct kvm_vcpu *vcpu;



	if (!kvm_arm_support_pmu_v3() || !has_vhe())

	if (!system_supports_pmuv3() || !has_vhe())

		return false;



	vcpu = kvm_get_running_vcpu();