Commit 6f9323f6 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S 



The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
SERDES which are individually muxed across different peripherals.

LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
muxed between PCIe and CPSW.

Define the lane-muxing macros to be used as the idle state values.

Co-developed-by: default avatarRavi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: default avatarRavi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: default avatarRoger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-6-s-vadapalli@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 18fb2b7c

arch/arm64/boot/dts/ti/k3-serdes.h

+8 −0
Original line number Diff line number Diff line
@@ -201,4 +201,12 @@ 
#define J784S4_SERDES4_LANE3_USB		0x2

#define J784S4_SERDES4_LANE3_IP4_UNUSED		0x3



/* J722S */



#define J722S_SERDES0_LANE0_USB			0x0

#define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1



#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0

#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1



#endif /* DTS_ARM64_TI_K3_SERDES_H */