Commit 6f9d713f authored by Vinod Koul's avatar Vinod Koul
Browse files

Merge branch 'fixes' into next 

This brings rockchip,pcie3-phy changes into next which incoming patches
are dependent on
parents 0338e1d2 47b3e2f3

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+4 −2
Original line number Diff line number Diff line
@@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
		/* Source clock from SoC internal PLL */

		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);

		if (imx8_phy->drvdata->variant != IMX8MM) {

			writel(AUX_PLL_REFCLK_SEL_SYS_PLL,

			       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);

		}

		val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;

		writel(val | ANA_AUX_RX_TERM_GND_EN,

		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

+5 −4
Original line number Diff line number Diff line
@@ -603,7 +603,7 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 
	u16 val;



	fix_idx = 0;

	for (addr = 0; addr < 512; addr++) {

	for (addr = 0; addr < ARRAY_SIZE(gbe_phy_init); addr++) {

		/*

		 * All PHY register values are defined in full for 3.125Gbps

		 * SERDES speed. The values required for 1.25 Gbps are almost
@@ -611,10 +611,11 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 
		 * comparison to 3.125 Gbps values. These register values are

		 * stored in "gbe_phy_init_fix" array.

		 */

		if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {

		if (!is_1gbps &&

		    fix_idx < ARRAY_SIZE(gbe_phy_init_fix) &&

		    gbe_phy_init_fix[fix_idx].addr == addr) {

			/* Use new value */

			val = gbe_phy_init_fix[fix_idx].value;

			if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))

			fix_idx++;

		} else {

			val = gbe_phy_init[addr];

drivers/phy/qualcomm/phy-qcom-m31.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ static int m31usb_phy_probe(struct platform_device *pdev) 
		return dev_err_probe(dev, PTR_ERR(qphy->phy),

				     "failed to create phy\n");



	qphy->vreg = devm_regulator_get(dev, "vdda-phy");

	qphy->vreg = devm_regulator_get(dev, "vdd");

	if (IS_ERR(qphy->vreg))

		return dev_err_probe(dev, PTR_ERR(qphy->vreg),

				     "failed to get vreg\n");

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+7 −3
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ enum qphy_reg_layout { 
	QPHY_COM_BIAS_EN_CLKBUFLR_EN,



	QPHY_DP_PHY_STATUS,

	QPHY_DP_PHY_VCO_DIV,



	QPHY_TX_TX_POL_INV,

	QPHY_TX_TX_DRV_LVL,
@@ -102,6 +103,7 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V3_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V3_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V3_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V3_TX_TX_DRV_LVL,
@@ -126,6 +128,7 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,



	[QPHY_DP_PHY_STATUS]		= QSERDES_V4_DP_PHY_STATUS,

	[QPHY_DP_PHY_VCO_DIV]		= QSERDES_V4_DP_PHY_VCO_DIV,



	[QPHY_TX_TX_POL_INV]		= QSERDES_V4_TX_TX_POL_INV,

	[QPHY_TX_TX_DRV_LVL]		= QSERDES_V4_TX_TX_DRV_LVL,
@@ -2202,9 +2205,9 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 
	writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);



	if (reverse)

		writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);

		writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);

	else

		writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);

		writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);



	return reverse;

}
@@ -2214,6 +2217,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 
	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;

	u32 phy_vco_div;

	unsigned long pixel_freq;

	const struct qmp_phy_cfg *cfg = qmp->cfg;



	switch (dp_opts->link_rate) {

	case 1620:
@@ -2236,7 +2240,7 @@ static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 
		/* Other link rates aren't supported */

		return -EINVAL;

	}

	writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);

	writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);



	clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);

	clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);

drivers/phy/rockchip/phy-rockchip-naneng-combphy.c

+33 −3
Original line number Diff line number Diff line
@@ -125,12 +125,15 @@ struct rockchip_combphy_grfcfg { 
};



struct rockchip_combphy_cfg {

	unsigned int num_phys;

	unsigned int phy_ids[3];

	const struct rockchip_combphy_grfcfg *grfcfg;

	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);

};



struct rockchip_combphy_priv {

	u8 type;

	int id;

	void __iomem *mmio;

	int num_clks;

	struct clk_bulk_data *clks;
@@ -320,7 +323,7 @@ static int rockchip_combphy_probe(struct platform_device *pdev) 
	struct rockchip_combphy_priv *priv;

	const struct rockchip_combphy_cfg *phy_cfg;

	struct resource *res;

	int ret;

	int ret, id;



	phy_cfg = of_device_get_match_data(dev);

	if (!phy_cfg) {
@@ -338,6 +341,15 @@ static int rockchip_combphy_probe(struct platform_device *pdev) 
		return ret;

	}



	/* find the phy-id from the io address */

	priv->id = -ENODEV;

	for (id = 0; id < phy_cfg->num_phys; id++) {

		if (res->start == phy_cfg->phy_ids[id]) {

			priv->id = id;

			break;

		}

	}



	priv->dev = dev;

	priv->type = PHY_NONE;

	priv->cfg = phy_cfg;
@@ -562,6 +574,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 
};



static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {

	.num_phys = 3,

	.phy_ids = {

		0xfe820000,

		0xfe830000,

		0xfe840000,

	},

	.grfcfg		= &rk3568_combphy_grfcfgs,

	.combphy_cfg	= rk3568_combphy_cfg,

};
@@ -578,9 +596,15 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) 
		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);

		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);

		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);

		switch (priv->id) {

		case 1:

			rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);

			break;

		case 2:

			rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);

			break;

		}

		break;

	case PHY_TYPE_USB3:

		/* Set SSC downward spread spectrum */

		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
@@ -736,6 +760,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { 
};



static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {

	.num_phys = 3,

	.phy_ids = {

		0xfee00000,

		0xfee10000,

		0xfee20000,

	},

	.grfcfg		= &rk3588_combphy_grfcfgs,

	.combphy_cfg	= rk3588_combphy_cfg,

};