Commit 6fdcb101 authored by Rahul T R's avatar Rahul T R Committed by Nishanth Menon
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arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX 



TI's J721E SoC supports a DPI to DSI video signal conversion bridge on
it's platform bus. The IP is from Cadence, and it has a custom TI
wrapper around it to facilitate integration.

This IP takes the DPI video signals from DSS and alongwith the DPHY IP,
it transmits DSI video signals out of the SoC.

Add support for DSI bridge and the DPHY-TX.

Signed-off-by: default avatarRahul T R <r-ravikumar@ti.com>
Signed-off-by: default avatarJayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: default avatarHarikrishna Shenoy <h-shenoy@ti.com>
Link: https://patch.msgid.link/20250905094325.472473-1-h-shenoy@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent 2e79ee4d

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -1887,6 +1887,45 @@ port@4 { 
		};

	};



	dphy2: phy@4480000 {

		compatible = "ti,j721e-dphy";

		reg = <0x00 0x04480000 0x00 0x1000>;

		clocks = <&k3_clks 296 1>, <&k3_clks 296 3>;

		clock-names = "psm", "pll_ref";

		#phy-cells = <0>;

		power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;

		assigned-clocks = <&k3_clks 296 3>;

		assigned-clock-parents = <&k3_clks 296 4>;

		assigned-clock-rates = <19200000>;

		status = "disabled";

	};



	dsi0: dsi@4800000 {

		compatible = "ti,j721e-dsi";

		reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>;

		clocks = <&k3_clks 150 1>, <&k3_clks 150 5>;

		clock-names = "dsi_p_clk", "dsi_sys_clk";

		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;

		interrupt-parent = <&gic500>;

		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&dphy2>;

		phy-names = "dphy";

		status = "disabled";



		dsi0_ports: ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

			};



			port@1 {

				reg = <1>;

			};

		};

	};



	dss: dss@4a00000 {

		compatible = "ti,j721e-dss";

		reg =