Commit 6fe8f9c1 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/wm: convert skl_watermark.h external interfaces to struct intel_display 



Going forward, struct intel_display is the main display device data
pointer. Convert the skl_watermark.h interface to struct intel_display.

Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/cd2b1863dee25b69b4766090dd183a7467c4edea.1744119460.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent b4bd4f21

drivers/gpu/drm/i915/display/intel_bw.c

+9 −15
Original line number Diff line number Diff line
@@ -976,7 +976,6 @@ static int mtl_find_qgv_points(struct intel_display *display, 
			       unsigned int num_active_planes,

			       struct intel_bw_state *new_bw_state)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	unsigned int best_rate = UINT_MAX;

	unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

	unsigned int qgv_peak_bw  = 0;
@@ -992,7 +991,7 @@ static int mtl_find_qgv_points(struct intel_display *display, 
	 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is

	 * not enabled. PM Demand code will clamp the value for the register

	 */

	if (!intel_can_enable_sagv(i915, new_bw_state)) {

	if (!intel_can_enable_sagv(display, new_bw_state)) {

		new_bw_state->qgv_point_peakbw = U16_MAX;

		drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");

		return 0;
@@ -1049,7 +1048,6 @@ static int icl_find_qgv_points(struct intel_display *display, 
			       const struct intel_bw_state *old_bw_state,

			       struct intel_bw_state *new_bw_state)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	unsigned int num_psf_gv_points = display->bw.max[0].num_psf_gv_points;

	unsigned int num_qgv_points = display->bw.max[0].num_qgv_points;

	u16 psf_points = 0;
@@ -1106,7 +1104,7 @@ static int icl_find_qgv_points(struct intel_display *display, 
	 * we can't enable SAGV due to the increased memory latency it may

	 * cause.

	 */

	if (!intel_can_enable_sagv(i915, new_bw_state)) {

	if (!intel_can_enable_sagv(display, new_bw_state)) {

		qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);

		drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",

			    qgv_points);
@@ -1195,8 +1193,7 @@ static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw, 
				   unsigned int data_rate)

{

	struct intel_display *display = to_intel_display(crtc);

	struct drm_i915_private *i915 = to_i915(display->drm);

	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);

	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);

	enum dbuf_slice slice;



	/*
@@ -1446,7 +1443,6 @@ static int intel_bw_modeset_checks(struct intel_atomic_state *state) 
static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)

{

	struct intel_display *display = to_intel_display(state);

	struct drm_i915_private *i915 = to_i915(display->drm);

	const struct intel_crtc_state *old_crtc_state;

	const struct intel_crtc_state *new_crtc_state;

	const struct intel_bw_state *old_bw_state = NULL;
@@ -1475,8 +1471,8 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state) 
	if (!new_bw_state)

		return 0;



	if (intel_can_enable_sagv(i915, new_bw_state) !=

	    intel_can_enable_sagv(i915, old_bw_state)) {

	if (intel_can_enable_sagv(display, new_bw_state) !=

	    intel_can_enable_sagv(display, old_bw_state)) {

		ret = intel_atomic_serialize_global_state(&new_bw_state->base);

		if (ret)

			return ret;
@@ -1492,13 +1488,12 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state) 
int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)

{

	struct intel_display *display = to_intel_display(state);

	struct drm_i915_private *i915 = to_i915(display->drm);

	bool changed = false;

	struct intel_bw_state *new_bw_state;

	const struct intel_bw_state *old_bw_state;

	int ret;



	if (DISPLAY_VER(i915) < 9)

	if (DISPLAY_VER(display) < 9)

		return 0;



	if (any_ms) {
@@ -1523,8 +1518,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms) 
	new_bw_state = intel_atomic_get_new_bw_state(state);



	if (new_bw_state &&

	    intel_can_enable_sagv(i915, old_bw_state) !=

	    intel_can_enable_sagv(i915, new_bw_state))

	    intel_can_enable_sagv(display, old_bw_state) !=

	    intel_can_enable_sagv(display, new_bw_state))

		changed = true;



	/*
@@ -1628,7 +1623,6 @@ static const struct intel_global_state_funcs intel_bw_funcs = { 


int intel_bw_init(struct intel_display *display)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct intel_bw_state *state;



	state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -1642,7 +1636,7 @@ int intel_bw_init(struct intel_display *display) 
	 * Limit this only if we have SAGV. And for Display version 14 onwards

	 * sagv is handled though pmdemand requests

	 */

	if (intel_has_sagv(i915) && IS_DISPLAY_VER(display, 11, 13))

	if (intel_has_sagv(display) && IS_DISPLAY_VER(display, 11, 13))

		icl_force_disable_sagv(display, state);



	return 0;

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −3
Original line number Diff line number Diff line
@@ -1972,9 +1972,7 @@ int intel_mdclk_cdclk_ratio(struct intel_display *display, 
static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,

					     const struct intel_cdclk_config *cdclk_config)

{

	struct drm_i915_private *i915 = to_i915(display->drm);



	intel_dbuf_mdclk_cdclk_ratio_update(i915,

	intel_dbuf_mdclk_cdclk_ratio_update(display,

					    intel_mdclk_cdclk_ratio(display, cdclk_config),

					    cdclk_config->joined_mbus);

}

drivers/gpu/drm/i915/display/intel_display.c

+1 −3
Original line number Diff line number Diff line
@@ -4162,8 +4162,6 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 
static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	const struct drm_display_mode *pipe_mode =

		&crtc_state->hw.pipe_mode;

	int linetime_wm;
@@ -4176,7 +4174,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 


	/* Display WA #1135: BXT:ALL GLK:ALL */

	if ((display->platform.geminilake || display->platform.broxton) &&

	    skl_watermark_ipc_enabled(dev_priv))

	    skl_watermark_ipc_enabled(display))

		linetime_wm /= 2;



	return min(linetime_wm, 0x1ff);

drivers/gpu/drm/i915/display/intel_display_driver.c

+3 −5
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ int intel_display_driver_probe_noirq(struct intel_display *display) 
	if (ret)

		goto cleanup_vga_client_pw_domain_dmc;



	ret = intel_dbuf_init(i915);

	ret = intel_dbuf_init(display);

	if (ret)

		goto cleanup_vga_client_pw_domain_dmc;
@@ -491,7 +491,6 @@ int intel_display_driver_probe_nogem(struct intel_display *display) 
/* part #3: call after gem init */

int intel_display_driver_probe(struct intel_display *display)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	int ret;



	if (!HAS_DISPLAY(display))
@@ -519,7 +518,7 @@ int intel_display_driver_probe(struct intel_display *display) 
	/* Only enable hotplug handling once the fbdev is fully set up. */

	intel_hpd_init(display);



	skl_watermark_ipc_init(i915);

	skl_watermark_ipc_init(display);



	return 0;

}
@@ -726,7 +725,6 @@ __intel_display_driver_resume(struct intel_display *display, 


void intel_display_driver_resume(struct intel_display *display)

{

	struct drm_i915_private *i915 = to_i915(display->drm);

	struct drm_atomic_state *state = display->restore.modeset_state;

	struct drm_modeset_acquire_ctx ctx;

	int ret;
@@ -754,7 +752,7 @@ void intel_display_driver_resume(struct intel_display *display) 
	if (!ret)

		ret = __intel_display_driver_resume(display, state, &ctx);



	skl_watermark_ipc_update(i915);

	skl_watermark_ipc_update(display);

	drm_modeset_drop_locks(&ctx);

	drm_modeset_acquire_fini(&ctx);

drivers/gpu/drm/i915/display/intel_dsb.c

+2 −2
Original line number Diff line number Diff line
@@ -143,10 +143,10 @@ static int dsb_vtotal(struct intel_atomic_state *state, 
static int dsb_dewake_scanline_start(struct intel_atomic_state *state,

				     struct intel_crtc *crtc)

{

	struct intel_display *display = to_intel_display(state);

	const struct intel_crtc_state *crtc_state =

		intel_pre_commit_crtc_state(state, crtc);

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	unsigned int latency = skl_watermark_max_latency(i915, 0);

	unsigned int latency = skl_watermark_max_latency(display, 0);



	return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) -

		intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency);