Commit 7009646d authored by Jie Gan's avatar Jie Gan Committed by Suzuki K Poulose
Browse files

dt-binding: Update oss email address for Coresight documents 



Update the OSS email addresses across all Coresight documents, as the
previous addresses have been deprecated.

Signed-off-by: default avatarJie Gan <jie.gan@oss.qualcomm.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250902042143.1010-1-jie.gan@oss.qualcomm.com
parent 8f0b4cce

Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source

+2 −2
Original line number Diff line number Diff line 
What:		/sys/bus/coresight/devices/dummy_source<N>/enable_source

Date:		Dec 2024

KernelVersion:	6.14

Contact:	Mao Jinlong <quic_jinlmao@quicinc.com>

Contact:	Mao Jinlong <jinlong.mao@oss.qualcomm.com>

Description:	(RW) Enable/disable tracing of dummy source. A sink should be activated

		before enabling the source. The path of coresight components linking

		the source to the sink is configured and managed automatically by the
@@ -10,7 +10,7 @@ Description: (RW) Enable/disable tracing of dummy source. A sink should be activ 
What:		/sys/bus/coresight/devices/dummy_source<N>/traceid

Date:		Dec 2024

KernelVersion:	6.14

Contact:	Mao Jinlong <quic_jinlmao@quicinc.com>

Contact:	Mao Jinlong <jinlong.mao@oss.qualcomm.com>

Description:	(R) Show the trace ID that will appear in the trace stream

		coming from this trace entity.

Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm

+28 −28
Original line number Diff line number Diff line 
What:		/sys/bus/coresight/devices/<tpdm-name>/integration_test

Date:		January 2023

KernelVersion:	6.2

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(Write) Run integration test for tpdm. Integration test

		will generate test data for tpdm. It can help to make
@@ -15,7 +15,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/reset_dataset

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(Write) Reset the dataset of the tpdm.
@@ -25,7 +25,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the trigger type of the DSB for tpdm.
@@ -36,7 +36,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the trigger timestamp of the DSB for tpdm.
@@ -47,7 +47,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_mode

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the programming mode of the DSB for tpdm.
@@ -61,7 +61,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the index number of the edge detection for the DSB

		subunit TPDM. Since there are at most 256 edge detections, this
@@ -70,7 +70,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		Write a data to control the edge detection corresponding to

		the index number. Before writing data to this sysfs file,
@@ -86,7 +86,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		Write a data to mask the edge detection corresponding to the index

		number. Before writing data to this sysfs file, "ctrl_idx" should
@@ -98,21 +98,21 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		Read a set of the edge control value of the DSB in TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		Read a set of the edge control mask of the DSB in TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the value of the trigger pattern for the DSB

		subunit TPDM.
@@ -120,7 +120,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the mask of the trigger pattern for the DSB

		subunit TPDM.
@@ -128,21 +128,21 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the value of the pattern for the DSB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(Write) Set the pattern timestamp of DSB tpdm. Read

		the pattern timestamp of DSB tpdm.
@@ -154,7 +154,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(Write) Set the pattern type of DSB tpdm. Read

		the pattern type of DSB tpdm.
@@ -166,7 +166,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]

Date:		March 2023

KernelVersion:	6.7

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the MSR(mux select register) for the DSB subunit

		TPDM.
@@ -174,7 +174,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_mode

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:	(Write) Set the data collection mode of CMB tpdm. Continuous

		change creates CMB data set elements on every CMBCLK edge.

		Trace-on-change creates CMB data set elements only when a new
@@ -188,7 +188,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the value of the trigger pattern for the CMB

		subunit TPDM.
@@ -196,7 +196,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the mask of the trigger pattern for the CMB

		subunit TPDM.
@@ -204,21 +204,21 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the value of the pattern for the CMB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the mask of the pattern for the CMB subunit TPDM.



What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(Write) Set the pattern timestamp of CMB tpdm. Read

		the pattern timestamp of CMB tpdm.
@@ -230,7 +230,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the trigger timestamp of the CMB for tpdm.
@@ -241,7 +241,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Read or write the status of timestamp upon all interface.

		Only value 0 and 1  can be written to this node. Set this node to 1 to request
@@ -253,7 +253,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]

Date:		January 2024

KernelVersion:	6.9

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the MSR(mux select register) for the CMB subunit

		TPDM.
@@ -261,7 +261,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane

Date:		Feb 2025

KernelVersion	6.15

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get which lane participates in the output pattern

		match cross trigger mechanism for the MCMB subunit TPDM.
@@ -269,7 +269,7 @@ Description: 
What:		/sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select

Date:		Feb 2025

KernelVersion	6.15

Contact:	Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>

Contact:	Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>

Description:

		(RW) Set/Get the enablement of the individual lane.

Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ maintainers: 
  - Mike Leach <mike.leach@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>

  - James Clark <james.clark@linaro.org>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Mao Jinlong <jinlong.mao@oss.qualcomm.com>

  - Hao Zhang <quic_hazha@quicinc.com>



properties:

Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ maintainers: 
  - Mike Leach <mike.leach@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>

  - James Clark <james.clark@linaro.org>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Mao Jinlong <jinlong.mao@oss.qualcomm.com>

  - Hao Zhang <quic_hazha@quicinc.com>



properties:

Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml

+3 −3
Original line number Diff line number Diff line
@@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: CoreSight TMC Control Unit



maintainers:

  - Yuanfang Zhang <quic_yuanfang@quicinc.com>

  - Mao Jinlong <quic_jinlmao@quicinc.com>

  - Jie Gan <quic_jiegan@quicinc.com>

  - Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>

  - Mao Jinlong <jinlong.mao@oss.qualcomm.com>

  - Jie Gan <jie.gan@oss.qualcomm.com>



description: |

  The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),