Commit 70109bcd authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operations 



TLBI IPAS2E1* are the last class of TLBI instructions we need
to handle. For each matching S2 MMU context, we invalidate a
range corresponding to the largest possible mapping for that
context.

At this stage, we don't handle TTL, which means we are likely
over-invalidating. Further patches will aim at making this
a bit better.

Co-developed-by: default avatarJintack Lim <jintack.lim@linaro.org>
Co-developed-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Signed-off-by: default avatarJintack Lim <jintack.lim@linaro.org>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240614144552.2773592-11-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 5cfb6cec

arch/arm64/kvm/sys_regs.c

+96 −0
Original line number Diff line number Diff line
@@ -2780,6 +2780,31 @@ static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

}



static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr)

{

	struct kvm *kvm = vpcu->kvm;

	u8 CRm = sys_reg_CRm(instr);

	u8 Op2 = sys_reg_Op2(instr);



	if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&

	    !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))

		return false;



	if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&

	    !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))

		return false;



	if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&

	    !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))

		return false;



	if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&

	    !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))

		return false;



	return true;

}



/* Only defined here as this is an internal "abstraction" */

union tlbi_info {

	struct {
@@ -2829,6 +2854,72 @@ static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
	return true;

}



static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu,

			     const union tlbi_info *info)

{

	unsigned long max_size;

	u64 base_addr;



	/*

	 * We drop a number of things from the supplied value:

	 *

	 * - NS bit: we're non-secure only.

	 *

	 * - TTL field: We already have the granule size from the

	 *   VTCR_EL2.TG0 field, and the level is only relevant to the

	 *   guest's S2PT.

	 *

	 * - IPA[51:48]: We don't support 52bit IPA just yet...

	 *

	 * And of course, adjust the IPA to be on an actual address.

	 */

	base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;



	/* Compute the maximum extent of the invalidation */

	switch (mmu->tlb_vtcr & VTCR_EL2_TG0_MASK) {

	case VTCR_EL2_TG0_4K:

		max_size = SZ_1G;

		break;

	case VTCR_EL2_TG0_16K:

		max_size = SZ_32M;

		break;

	case VTCR_EL2_TG0_64K:

	default:	    /* IMPDEF: treat any other value as 64k */

		/*

		 * No, we do not support 52bit IPA in nested yet. Once

		 * we do, this should be 4TB.

		 */

		max_size = SZ_512M;

		break;

	}



	base_addr &= ~(max_size - 1);



	kvm_stage2_unmap_range(mmu, base_addr, max_size);

}



static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,

			     const struct sys_reg_desc *r)

{

	u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);

	u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);



	if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding)) {

		kvm_inject_undefined(vcpu);

		return false;

	}



	kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),

				   &(union tlbi_info) {

					   .ipa = {

						   .addr = p->regval,

					   },

				   },

				   s2_mmu_unmap_ipa);



	return true;

}



static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu,

			     const union tlbi_info *info)

{
@@ -2903,8 +2994,13 @@ static struct sys_reg_desc sys_insn_descs[] = { 
	SYS_INSN(TLBI_VALE1, handle_tlbi_el1),

	SYS_INSN(TLBI_VAALE1, handle_tlbi_el1),



	SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),

	SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is),



	SYS_INSN(TLBI_ALLE1IS, handle_alle1is),

	SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is),

	SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is),

	SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is),

	SYS_INSN(TLBI_ALLE1, handle_alle1is),

	SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is),

};