Commit 701d0e91 authored by Peter Griffin's avatar Peter Griffin Committed by Krzysztof Kozlowski
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pinctrl: samsung: add support for eint_fltcon_offset 



On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a
fixed offset like previous SoCs as the fltcon1 register only exists when
there are more than 4 pins in the bank.

Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take
an additional fltcon_offs variable.

This can then be used in suspend/resume callbacks to save and restore
the fltcon0 and fltcon1 registers.

Fixes: 4a8be01a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration")
Cc: stable@vger.kernel.org
Reviewed-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250307-pinctrl-fltcon-suspend-v4-1-2d775e486036@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent eb76dc97

drivers/pinctrl/samsung/pinctrl-exynos-arm64.c

+49 −49
Original line number Diff line number Diff line
@@ -1677,83 +1677,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { 


/* pin banks of gs101 pin-controller (ALIVE) */

static const struct samsung_pin_bank_data gs101_pin_alive[] = {

	EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),

	EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),

	EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),

	EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),

	EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),

	EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),

	EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),

	EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),

	GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00),

	GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08),

	GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10),

	GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18),

	GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c),

	GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20),

	GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28),

	GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30),

};



/* pin banks of gs101 pin-controller (FAR_ALIVE) */

static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {

	EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),

	EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),

	EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),

	EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),

	GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00),

	GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08),

	GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c),

	GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14),

};



/* pin banks of gs101 pin-controller (GSACORE) */

static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {

	EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),

	GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00),

	GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04),

	GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c),

};



/* pin banks of gs101 pin-controller (GSACTRL) */

static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {

	EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),

	GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00),

};



/* pin banks of gs101 pin-controller (PERIC0) */

static const struct samsung_pin_bank_data gs101_pin_peric0[] = {

	EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),

	EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),

	EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),

	EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),

	EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),

	EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),

	EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),

	EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),

	EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),

	EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),

	EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),

	EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),

	EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),

	EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),

	EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),

	EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),

	EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),

	EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),

	EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),

	GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00),

	GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08),

	GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c),

	GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10),

	GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14),

	GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18),

	GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c),

	GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20),

	GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24),

	GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28),

	GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c),

	GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30),

	GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34),

	GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38),

	GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c),

	GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40),

	GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44),

	GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48),

	GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c),

	GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50),

};



/* pin banks of gs101 pin-controller (PERIC1) */

static const struct samsung_pin_bank_data gs101_pin_peric1[] = {

	EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),

	EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),

	EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),

	EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),

	EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),

	EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),

	EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),

	EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),

	GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00),

	GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08),

	GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c),

	GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10),

	GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18),

	GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c),

	GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20),

	GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28),

};



/* pin banks of gs101 pin-controller (HSI1) */

static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {

	EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),

	EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),

	GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00),

	GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08),

};



/* pin banks of gs101 pin-controller (HSI2) */

static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {

	EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),

	EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),

	EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),

	GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00),

	GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08),

	GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c),

};



static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {

drivers/pinctrl/samsung/pinctrl-exynos.h

+22 −0
Original line number Diff line number Diff line
@@ -194,6 +194,28 @@ 
		.name			= id				\

	}



#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \

	{							\

		.type			= &exynos850_bank_type_off,	\

		.pctl_offset		= reg,			\

		.nr_pins		= pins,			\

		.eint_type		= EINT_TYPE_GPIO,	\

		.eint_offset		= offs,			\

		.eint_fltcon_offset	= fltcon_offs,		\

		.name			= id			\

	}



#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \

	{								\

		.type			= &exynos850_bank_type_alive,	\

		.pctl_offset		= reg,				\

		.nr_pins		= pins,				\

		.eint_type		= EINT_TYPE_WKUP,		\

		.eint_offset		= offs,				\

		.eint_fltcon_offset	= fltcon_offs,			\

		.name			= id				\

	}



/**

 * struct exynos_weint_data: irq specific data for all the wakeup interrupts

 * generated by the external wakeup interrupt controller.

drivers/pinctrl/samsung/pinctrl-samsung.c

+1 −0
Original line number Diff line number Diff line
@@ -1230,6 +1230,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, 
		bank->eint_con_offset = bdata->eint_con_offset;

		bank->eint_mask_offset = bdata->eint_mask_offset;

		bank->eint_pend_offset = bdata->eint_pend_offset;

		bank->eint_fltcon_offset = bdata->eint_fltcon_offset;

		bank->name = bdata->name;



		raw_spin_lock_init(&bank->slock);

drivers/pinctrl/samsung/pinctrl-samsung.h

+4 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ struct samsung_pin_bank_type { 
 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.

 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.

 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.

 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.

 * @name: name to be prefixed for each pin in this pin bank.

 */

struct samsung_pin_bank_data {
@@ -158,6 +159,7 @@ struct samsung_pin_bank_data { 
	u32		eint_con_offset;

	u32		eint_mask_offset;

	u32		eint_pend_offset;

	u32		eint_fltcon_offset;

	const char	*name;

};
@@ -175,6 +177,7 @@ struct samsung_pin_bank_data { 
 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.

 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.

 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.

 * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.

 * @name: name to be prefixed for each pin in this pin bank.

 * @id: id of the bank, propagated to the pin range.

 * @pin_base: starting pin number of the bank.
@@ -201,6 +204,7 @@ struct samsung_pin_bank { 
	u32		eint_con_offset;

	u32		eint_mask_offset;

	u32		eint_pend_offset;

	u32		eint_fltcon_offset;

	const char	*name;

	u32		id;