Loading arch/parisc/kernel/firmware.c +2 −2 Original line number Diff line number Diff line Loading @@ -634,7 +634,7 @@ EXPORT_SYMBOL(pdc_lan_station_id); * pdc_stable_read - Read data from Stable Storage. * @staddr: Stable Storage address to access. * @memaddr: The memory address where Stable Storage data shall be copied. * @count: number of bytes to transfert. count is multiple of 4. * @count: number of bytes to transfer. count is multiple of 4. * * This PDC call reads from the Stable Storage address supplied in staddr * and copies count bytes to the memory address memaddr. Loading @@ -660,7 +660,7 @@ EXPORT_SYMBOL(pdc_stable_read); * pdc_stable_write - Write data to Stable Storage. * @staddr: Stable Storage address to access. * @memaddr: The memory address where Stable Storage data shall be read from. * @count: number of bytes to transfert. count is multiple of 4. * @count: number of bytes to transfer. count is multiple of 4. * * This PDC call reads count bytes from the supplied memaddr address, * and copies count bytes to the Stable Storage address staddr. Loading arch/parisc/kernel/perf.c +6 −6 Original line number Diff line number Diff line Loading @@ -576,27 +576,27 @@ static int perf_stop_counters(uint32_t *raddr) if (!perf_rdr_read_ubuf(16, userbuf)) return -13; /* Counter0 is bits 1398 thru 1429 */ /* Counter0 is bits 1398 to 1429 */ tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; /* OR sticky0 (bit 1430) to counter0 bit 32 */ tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; raddr[0] = (uint32_t)tmp64; /* Counter1 is bits 1431 thru 1462 */ /* Counter1 is bits 1431 to 1462 */ tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; /* OR sticky1 (bit 1463) to counter1 bit 32 */ tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; raddr[1] = (uint32_t)tmp64; /* Counter2 is bits 1464 thru 1495 */ /* Counter2 is bits 1464 to 1495 */ tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; /* OR sticky2 (bit 1496) to counter2 bit 32 */ tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; raddr[2] = (uint32_t)tmp64; /* Counter3 is bits 1497 thru 1528 */ /* Counter3 is bits 1497 to 1528 */ tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; /* OR sticky3 (bit 1529) to counter3 bit 32 */ tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; Loading @@ -618,7 +618,7 @@ static int perf_stop_counters(uint32_t *raddr) userbuf[23] = 0; /* * Write back the zero'ed bytes + the image given * Write back the zeroed bytes + the image given * the read was destructive. */ perf_rdr_write(16, userbuf); Loading arch/parisc/kernel/processor.c +4 −4 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ extern int update_cr16_clocksource(void); /* from time.c */ ** will call register_parisc_driver(&cpu_driver) before calling do_inventory(). ** ** The goal of consolidating CPU initialization into one place is ** to make sure all CPU's get initialized the same way. ** to make sure all CPUs get initialized the same way. ** The code path not shared is how PDC hands control of the CPU to the OS. ** The initialization of OS data structures is the same (done below). */ Loading Loading @@ -166,7 +166,7 @@ static int __init processor_probe(struct parisc_device *dev) #endif /* ** CONFIG_SMP: init_smp_config() will attempt to get CPU's into ** CONFIG_SMP: init_smp_config() will attempt to get CPUs into ** OS control. RENDEZVOUS is the default state - see mem_set above. ** p->state = STATE_RENDEZVOUS; */ Loading Loading @@ -334,7 +334,7 @@ int __init init_per_cpu(int cpunum) } /* * Display cpu info for all cpu's. * Display CPU info for all CPUs. */ int show_cpuinfo (struct seq_file *m, void *v) Loading Loading @@ -393,7 +393,7 @@ static struct parisc_driver cpu_driver __read_mostly = { }; /** * processor_init - Processor initalization procedure. * processor_init - Processor initialization procedure. * * Register this driver. */ Loading arch/parisc/kernel/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ void __init setup_arch(char **cmdline_p) } /* * Display cpu info for all cpu's. * Display CPU info for all CPUs. * for parisc this is in processor.c */ extern int show_cpuinfo (struct seq_file *m, void *v); Loading arch/parisc/kernel/smp.c +3 −3 Original line number Diff line number Diff line Loading @@ -419,7 +419,7 @@ smp_cpu_init(int cpunum) BUG(); enter_lazy_tlb(&init_mm, current); init_IRQ(); /* make sure no IRQ's are enabled or pending */ init_IRQ(); /* make sure no IRQs are enabled or pending */ start_cpu_itimer(); } Loading Loading @@ -552,7 +552,7 @@ void __devinit smp_prepare_boot_cpu(void) /* ** inventory.c:do_inventory() hasn't yet been run and thus we ** don't 'discover' the additional CPU's until later. ** don't 'discover' the additional CPUs until later. */ void __init smp_prepare_cpus(unsigned int max_cpus) { Loading Loading
arch/parisc/kernel/firmware.c +2 −2 Original line number Diff line number Diff line Loading @@ -634,7 +634,7 @@ EXPORT_SYMBOL(pdc_lan_station_id); * pdc_stable_read - Read data from Stable Storage. * @staddr: Stable Storage address to access. * @memaddr: The memory address where Stable Storage data shall be copied. * @count: number of bytes to transfert. count is multiple of 4. * @count: number of bytes to transfer. count is multiple of 4. * * This PDC call reads from the Stable Storage address supplied in staddr * and copies count bytes to the memory address memaddr. Loading @@ -660,7 +660,7 @@ EXPORT_SYMBOL(pdc_stable_read); * pdc_stable_write - Write data to Stable Storage. * @staddr: Stable Storage address to access. * @memaddr: The memory address where Stable Storage data shall be read from. * @count: number of bytes to transfert. count is multiple of 4. * @count: number of bytes to transfer. count is multiple of 4. * * This PDC call reads count bytes from the supplied memaddr address, * and copies count bytes to the Stable Storage address staddr. Loading
arch/parisc/kernel/perf.c +6 −6 Original line number Diff line number Diff line Loading @@ -576,27 +576,27 @@ static int perf_stop_counters(uint32_t *raddr) if (!perf_rdr_read_ubuf(16, userbuf)) return -13; /* Counter0 is bits 1398 thru 1429 */ /* Counter0 is bits 1398 to 1429 */ tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; /* OR sticky0 (bit 1430) to counter0 bit 32 */ tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; raddr[0] = (uint32_t)tmp64; /* Counter1 is bits 1431 thru 1462 */ /* Counter1 is bits 1431 to 1462 */ tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; /* OR sticky1 (bit 1463) to counter1 bit 32 */ tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; raddr[1] = (uint32_t)tmp64; /* Counter2 is bits 1464 thru 1495 */ /* Counter2 is bits 1464 to 1495 */ tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; /* OR sticky2 (bit 1496) to counter2 bit 32 */ tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; raddr[2] = (uint32_t)tmp64; /* Counter3 is bits 1497 thru 1528 */ /* Counter3 is bits 1497 to 1528 */ tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; /* OR sticky3 (bit 1529) to counter3 bit 32 */ tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; Loading @@ -618,7 +618,7 @@ static int perf_stop_counters(uint32_t *raddr) userbuf[23] = 0; /* * Write back the zero'ed bytes + the image given * Write back the zeroed bytes + the image given * the read was destructive. */ perf_rdr_write(16, userbuf); Loading
arch/parisc/kernel/processor.c +4 −4 Original line number Diff line number Diff line Loading @@ -63,7 +63,7 @@ extern int update_cr16_clocksource(void); /* from time.c */ ** will call register_parisc_driver(&cpu_driver) before calling do_inventory(). ** ** The goal of consolidating CPU initialization into one place is ** to make sure all CPU's get initialized the same way. ** to make sure all CPUs get initialized the same way. ** The code path not shared is how PDC hands control of the CPU to the OS. ** The initialization of OS data structures is the same (done below). */ Loading Loading @@ -166,7 +166,7 @@ static int __init processor_probe(struct parisc_device *dev) #endif /* ** CONFIG_SMP: init_smp_config() will attempt to get CPU's into ** CONFIG_SMP: init_smp_config() will attempt to get CPUs into ** OS control. RENDEZVOUS is the default state - see mem_set above. ** p->state = STATE_RENDEZVOUS; */ Loading Loading @@ -334,7 +334,7 @@ int __init init_per_cpu(int cpunum) } /* * Display cpu info for all cpu's. * Display CPU info for all CPUs. */ int show_cpuinfo (struct seq_file *m, void *v) Loading Loading @@ -393,7 +393,7 @@ static struct parisc_driver cpu_driver __read_mostly = { }; /** * processor_init - Processor initalization procedure. * processor_init - Processor initialization procedure. * * Register this driver. */ Loading
arch/parisc/kernel/setup.c +1 −1 Original line number Diff line number Diff line Loading @@ -162,7 +162,7 @@ void __init setup_arch(char **cmdline_p) } /* * Display cpu info for all cpu's. * Display CPU info for all CPUs. * for parisc this is in processor.c */ extern int show_cpuinfo (struct seq_file *m, void *v); Loading
arch/parisc/kernel/smp.c +3 −3 Original line number Diff line number Diff line Loading @@ -419,7 +419,7 @@ smp_cpu_init(int cpunum) BUG(); enter_lazy_tlb(&init_mm, current); init_IRQ(); /* make sure no IRQ's are enabled or pending */ init_IRQ(); /* make sure no IRQs are enabled or pending */ start_cpu_itimer(); } Loading Loading @@ -552,7 +552,7 @@ void __devinit smp_prepare_boot_cpu(void) /* ** inventory.c:do_inventory() hasn't yet been run and thus we ** don't 'discover' the additional CPU's until later. ** don't 'discover' the additional CPUs until later. */ void __init smp_prepare_cpus(unsigned int max_cpus) { Loading