Commit 7052e808 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64/sysreg: Get rid of the TCR2_EL1x SysregFields 



TCR2_EL1x is a pretty bizarre construct, as it is shared between
TCR2_EL1 and TCR2_EL12. But the latter is obviously only an
accessor to the former.

In order to make things more consistent, upgrade TCR2_EL1x to
a full-blown sysreg definition for TCR2_EL1, and describe TCR2_EL12
as a mapping to TCR2_EL1.

This results in a couple of minor changes to the actual code.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241219173351.1123087-3-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 078bc965

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -2375,7 +2375,7 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 
#ifdef CONFIG_ARM64_POE

static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)

{

	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);

	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);

	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);

}

#endif

arch/arm64/kvm/at.c

+3 −3
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static bool s1pie_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime) 
		return vcpu_read_sys_reg(vcpu, TCR2_EL2) & TCR2_EL2_PIE;

	case TR_EL10:

		return  (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TCR2En) &&

			(__vcpu_sys_reg(vcpu, TCR2_EL1) & TCR2_EL1x_PIE);

			(__vcpu_sys_reg(vcpu, TCR2_EL1) & TCR2_EL1_PIE);

	default:

		BUG();

	}
@@ -140,8 +140,8 @@ static void compute_s1poe(struct kvm_vcpu *vcpu, struct s1_walk_info *wi) 
		}



		val = __vcpu_sys_reg(vcpu, TCR2_EL1);

		wi->poe = val & TCR2_EL1x_POE;

		wi->e0poe = val & TCR2_EL1x_E0POE;

		wi->poe = val & TCR2_EL1_POE;

		wi->e0poe = val & TCR2_EL1_E0POE;

	}

}

arch/arm64/mm/proc.S

+3 −2
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ alternative_else_nop_endif 
#ifdef CONFIG_ARM64_HAFT

	cmp	x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT

	b.lt	1f

	orr	tcr2, tcr2, TCR2_EL1x_HAFT

	orr	tcr2, tcr2, TCR2_EL1_HAFT

#endif /* CONFIG_ARM64_HAFT */

1:

#endif	/* CONFIG_ARM64_HW_AFDBM */
@@ -532,7 +532,8 @@ alternative_else_nop_endif 
#undef PTE_MAYBE_NG

#undef PTE_MAYBE_SHARED



	orr	tcr2, tcr2, TCR2_EL1x_PIE

	orr	tcr2, tcr2, TCR2_EL1_PIE

	msr	REG_TCR2_EL1, x0



.Lskip_indirection:

arch/arm64/tools/sysreg

+2 −6
Original line number Diff line number Diff line
@@ -3000,7 +3000,7 @@ Sysreg TTBR1_EL1 3 0 2 0 1 
Fields	TTBRx_EL1

EndSysreg



SysregFields	TCR2_EL1x

Sysreg	TCR2_EL1	3	0	2	0	3

Res0	63:16

Field	15	DisCH1

Field	14	DisCH0
@@ -3014,14 +3014,10 @@ Field 3 POE 
Field	2	E0POE

Field	1	PIE

Field	0	PnCH

EndSysregFields



Sysreg	TCR2_EL1	3	0	2	0	3

Fields	TCR2_EL1x

EndSysreg



Sysreg	TCR2_EL12	3	5	2	0	3

Fields	TCR2_EL1x

Mapping	TCR2_EL1

EndSysreg



Sysreg	TCR2_EL2	3	4	2	0	3