Commit 7059fbeb authored by Thinh Nguyen's avatar Thinh Nguyen Committed by Greg Kroah-Hartman
Browse files

Revert "usb: dwc3: Soft reset phy on probe for host" 



This reverts commit 8bea147d.

The phy soft reset GUSB2PHYCFG.PHYSOFTRST only applies to UTMI phy, not
ULPI. This fix is incomplete.

Cc:  <stable@vger.kernel.org>
Fixes: 8bea147d ("usb: dwc3: Soft reset phy on probe for host")
Reported-by: default avatarKöry Maincent <kory.maincent@bootlin.com>
Closes: https://lore.kernel.org/linux-usb/20231205151959.5236c231@kmaincent-XPS-13-7390


Signed-off-by: default avatarThinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/29a26593a60eba727de872a3e580a674807b3339.1703282469.git.Thinh.Nguyen@synopsys.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ca2dc35e

drivers/usb/dwc3/core.c

+1 −38
Original line number Diff line number Diff line
@@ -279,46 +279,9 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) 
	 * XHCI driver will reset the host block. If dwc3 was configured for

	 * host-only mode or current role is host, then we can return early.

	 */

	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)

	if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)

		return 0;



	/*

	 * If the dr_mode is host and the dwc->current_dr_role is not the

	 * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode

	 * isn't executed yet. Ensure the phy is ready before the controller

	 * updates the GCTL.PRTCAPDIR or other settings by soft-resetting

	 * the phy.

	 *

	 * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n

	 * is port index. If this is a multiport host, then we need to reset

	 * all active ports.

	 */

	if (dwc->dr_mode == USB_DR_MODE_HOST) {

		u32 usb3_port;

		u32 usb2_port;



		usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

		usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;

		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);



		usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

		usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;

		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);



		/* Small delay for phy reset assertion */

		usleep_range(1000, 2000);



		usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;

		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);



		usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;

		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);



		/* Wait for clock synchronization */

		msleep(50);

		return 0;

	}



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);

	reg |= DWC3_DCTL_CSFTRST;

	reg &= ~DWC3_DCTL_RUN_STOP;