Unverified Commit 707472ac authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ti-k3-dt-for-v5.14' of... 

Merge tag 'ti-k3-dt-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt

Devicetree changes for TI K3 platforms for v5.14 merge window:

* New features:
  - AM64 gains PCIe and USB3 for am64-sk board, R5 remote proc (includes
    AM64 rproc bindings tag from Bjorn's  tree)
  - AM65, J721e gains ICSSG MDIO nodes
  - AM65: UHS mode speed enabled on am65
* Fixes:
  - Fixups on AM64 SRAM model thanks to a ROM bug for USB DFU mode
  - Schema related cleanups across j7*, am65, 64
  - Few misc Fixups on AM64 where MAC address could conflict; j7200 for
    USB2 Rx sensitivity etc.

* tag 'ti-k3-dt-for-v5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (37 commits)
  arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs
  arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
  arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
  arm64: dts: ti: k3-am64-main: Update TF-A load address to workaround USB DFU limitation
  arm64: dts: ti: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
  arm64: dts: ti: k3-am64-main: Update TF-A's maximum size and node name
  arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes
  arm64: dts: ti: k3-am642-evm: align ti,pindir-d0-out-d1-in property with dt-shema
  arm64: dts: ti: am65: align ti,pindir-d0-out-d1-in property with dt-shema
  arm64: dts: ti: k3-am642-main: fix ports mac properties
  arm64: dts: ti: iot2050: Configure r5f cluster on basic variant in split mode
  arm64: dts: ti: k3-am642-sk: Disable PCIe
  arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
  arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
  arm64: dts: ti: k3-am64-main: Add PCIe DT node
  arm64: dts: ti: k3-am64-main: Add SERDES DT node
  arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"
  arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES
  arm64: dts: ti: k3-j721e-main: Add #clock-cells property to serdes DT node
  arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
  ...

Link: https://lore.kernel.org/r/20210619000150.6ooqnxxsnsvncs5u@pushchair


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e356dc4c d71abfcc

Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml

+26 −5
Original line number Diff line number Diff line
@@ -14,8 +14,12 @@ description: | 
  processor subsystems/clusters (R5FSS). The dual core cluster can be used

  either in a LockStep mode providing safety/fault tolerance features or in a

  Split mode providing two individual compute cores for doubling the compute

  capacity. These are used together with other processors present on the SoC

  to achieve various system level goals.

  capacity on most SoCs. These are used together with other processors present

  on the SoC to achieve various system level goals.



  AM64x SoCs do not support LockStep mode, but rather a new non-safety mode

  called "Single-CPU" mode, where only Core0 is used, but with ability to use

  Core1's TCMs as well.



  Each Dual-Core R5F sub-system is represented as a single DTS node

  representing the cluster, with a pair of child DT nodes representing
@@ -33,6 +37,7 @@ properties: 
      - ti,am654-r5fss

      - ti,j721e-r5fss

      - ti,j7200-r5fss

      - ti,am64-r5fss



  power-domains:

    description: |
@@ -56,11 +61,12 @@ properties: 


  ti,cluster-mode:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1]

    description: |

      Configuration Mode for the Dual R5F cores within the R5F cluster.

      Should be either a value of 1 (LockStep mode) or 0 (Split mode),

      default is LockStep mode if omitted.

      Should be either a value of 1 (LockStep mode) or 0 (Split mode) on

      most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;

      and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)

      on AM64x SoCs, default is Split mode if omitted.



# R5F Processor Child Nodes:

# ==========================
@@ -97,6 +103,7 @@ patternProperties: 
          - ti,am654-r5f

          - ti,j721e-r5f

          - ti,j7200-r5f

          - ti,am64-r5f



      reg:

        items:
@@ -198,6 +205,20 @@ patternProperties: 


    unevaluatedProperties: false



if:

  properties:

    compatible:

      enum:

        - ti,am64-r5fss

then:

  properties:

    ti,cluster-mode:

      enum: [0, 2]

else:

  properties:

    ti,cluster-mode:

      enum: [0, 1]



required:

  - compatible

  - power-domains

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

+210 −23
Original line number Diff line number Diff line
@@ -5,6 +5,17 @@ 
 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/

 */



#include <dt-bindings/phy/phy-cadence.h>

#include <dt-bindings/phy/phy-ti.h>



/ {

	serdes_refclk: clock-cmnrefclk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <0>;

	};

};



&cbass_main {

	oc_sram: sram@70000000 {

		compatible = "mmio-sram";
@@ -13,8 +24,30 @@ oc_sram: sram@70000000 { 
		#size-cells = <1>;

		ranges = <0x0 0x00 0x70000000 0x200000>;



		atf-sram@0 {

			reg = <0x0 0x1a000>;

		tfa-sram@1c0000 {

			reg = <0x1c0000 0x20000>;

		};



		dmsc-sram@1e0000 {

			reg = <0x1e0000 0x1c000>;

		};



		sproxy-sram@1fc000 {

			reg = <0x1fc000 0x4000>;

		};

	};



	main_conf: syscon@43000000 {

		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";

		reg = <0x0 0x43000000 0x0 0x20000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x43000000 0x20000>;



		serdes_ln_ctrl: mux-controller {

			compatible = "mmio-mux";

			#mux-control-cells = <1>;

			mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */

		};

	};
@@ -42,12 +75,12 @@ gic_its: msi-controller@1820000 { 
		};

	};



	dmss: dmss {

	dmss: bus@48000000 {

		compatible = "simple-mfd";

		#address-cells = <2>;

		#size-cells = <2>;

		dma-ranges;

		ranges;

		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;



		ti,sci-dev-id = <25>;
@@ -134,7 +167,7 @@ main_pktdma: dma-controller@485c0000 { 
		};

	};



	dmsc: dmsc@44043000 {

	dmsc: system-controller@44043000 {

		compatible = "ti,k2g-sci";

		ti,host-id = <12>;

		mbox-names = "rx", "tx";
@@ -148,7 +181,7 @@ k3_pds: power-controller { 
			#power-domain-cells = <2>;

		};



		k3_clks: clocks {

		k3_clks: clock-controller {

			compatible = "ti,k2g-sci-clk";

			#clock-cells = <2>;

		};
@@ -189,8 +222,6 @@ phy_gmii_sel: phy@4044 { 
	main_uart0: serial@2800000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02800000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -202,8 +233,6 @@ main_uart0: serial@2800000 { 
	main_uart1: serial@2810000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02810000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -215,8 +244,6 @@ main_uart1: serial@2810000 { 
	main_uart2: serial@2820000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02820000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -228,8 +255,6 @@ main_uart2: serial@2820000 { 
	main_uart3: serial@2830000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02830000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -241,8 +266,6 @@ main_uart3: serial@2830000 { 
	main_uart4: serial@2840000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02840000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -254,8 +277,6 @@ main_uart4: serial@2840000 { 
	main_uart5: serial@2850000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02850000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -267,8 +288,6 @@ main_uart5: serial@2850000 { 
	main_uart6: serial@2860000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02860000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -373,8 +392,9 @@ main_spi4: spi@20140000 { 
		clocks = <&k3_clks 145 0>;

	};



	main_gpio_intr: interrupt-controller0 {

	main_gpio_intr: interrupt-controller@a00000 {

		compatible = "ti,sci-intr";

		reg = <0x00 0x00a00000 0x00 0x800>;

		ti,intr-trigger-type = <1>;

		interrupt-controller;

		interrupt-parent = <&gic500>;
@@ -488,7 +508,8 @@ cpsw_port1: port@1 { 
				ti,mac-only;

				label = "port1";

				phys = <&phy_gmii_sel 1>;

				mac-address = [00 00 de ad be ef];

				mac-address = [00 00 00 00 00 00];

				ti,syscon-efuse = <&main_conf 0x200>;

			};



			cpsw_port2: port@2 {
@@ -496,7 +517,7 @@ cpsw_port2: port@2 { 
				ti,mac-only;

				label = "port2";

				phys = <&phy_gmii_sel 2>;

				mac-address = [00 01 de ad be ef];

				mac-address = [00 00 00 00 00 00];

			};

		};
@@ -672,4 +693,170 @@ mailbox0_cluster7: mailbox@29070000 { 
		ti,mbox-num-users = <4>;

		ti,mbox-num-fifos = <16>;

	};



	main_r5fss0: r5fss@78000000 {

		compatible = "ti,am64-r5fss";

		ti,cluster-mode = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x78000000 0x00 0x78000000 0x10000>,

			 <0x78100000 0x00 0x78100000 0x10000>,

			 <0x78200000 0x00 0x78200000 0x08000>,

			 <0x78300000 0x00 0x78300000 0x08000>;

		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;



		main_r5fss0_core0: r5f@78000000 {

			compatible = "ti,am64-r5f";

			reg = <0x78000000 0x00010000>,

			      <0x78100000 0x00010000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <121>;

			ti,sci-proc-ids = <0x01 0xff>;

			resets = <&k3_reset 121 1>;

			firmware-name = "am64-main-r5f0_0-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};



		main_r5fss0_core1: r5f@78200000 {

			compatible = "ti,am64-r5f";

			reg = <0x78200000 0x00008000>,

			      <0x78300000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <122>;

			ti,sci-proc-ids = <0x02 0xff>;

			resets = <&k3_reset 122 1>;

			firmware-name = "am64-main-r5f0_1-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};

	};



	main_r5fss1: r5fss@78400000 {

		compatible = "ti,am64-r5fss";

		ti,cluster-mode = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x78400000 0x00 0x78400000 0x10000>,

			 <0x78500000 0x00 0x78500000 0x10000>,

			 <0x78600000 0x00 0x78600000 0x08000>,

			 <0x78700000 0x00 0x78700000 0x08000>;

		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;



		main_r5fss1_core0: r5f@78400000 {

			compatible = "ti,am64-r5f";

			reg = <0x78400000 0x00010000>,

			      <0x78500000 0x00010000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <123>;

			ti,sci-proc-ids = <0x06 0xff>;

			resets = <&k3_reset 123 1>;

			firmware-name = "am64-main-r5f1_0-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};



		main_r5fss1_core1: r5f@78600000 {

			compatible = "ti,am64-r5f";

			reg = <0x78600000 0x00008000>,

			      <0x78700000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <124>;

			ti,sci-proc-ids = <0x07 0xff>;

			resets = <&k3_reset 124 1>;

			firmware-name = "am64-main-r5f1_1-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};

	};



	serdes_wiz0: wiz@f000000 {

		compatible = "ti,am64-wiz-10g";

		#address-cells = <1>;

		#size-cells = <1>;

		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;

		clock-names = "fck", "core_ref_clk", "ext_ref_clk";

		num-lanes = <1>;

		#reset-cells = <1>;

		#clock-cells = <1>;

		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;



		assigned-clocks = <&k3_clks 162 1>;

		assigned-clock-parents = <&k3_clks 162 5>;



		serdes0: serdes@f000000 {

			compatible = "ti,j721e-serdes-10g";

			reg = <0x0f000000 0x00010000>;

			reg-names = "torrent_phy";

			resets = <&serdes_wiz0 0>;

			reset-names = "torrent_reset";

			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,

				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;

			clock-names = "refclk", "phy_en_refclk";

			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,

					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,

					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;

			assigned-clock-parents = <&k3_clks 162 1>,

						 <&k3_clks 162 1>,

						 <&k3_clks 162 1>;

			#address-cells = <1>;

			#size-cells = <0>;

			#clock-cells = <1>;

		};

	};



	pcie0_rc: pcie@f102000 {

		compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";

		reg = <0x00 0x0f102000 0x00 0x1000>,

		      <0x00 0x0f100000 0x00 0x400>,

		      <0x00 0x0d000000 0x00 0x00800000>,

		      <0x00 0x68000000 0x00 0x00001000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;

		device_type = "pci";

		ti,syscon-pcie-ctrl = <&main_conf 0x4070>;

		max-link-speed = <2>;

		num-lanes = <1>;

		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;

		clock-names = "fck", "pcie_refclk";

		#address-cells = <3>;

		#size-cells = <2>;

		bus-range = <0x0 0xff>;

		cdns,no-bar-match-nbits = <64>;

		vendor-id = <0x104c>;

		device-id = <0xb010>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,

			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;

	};



	pcie0_ep: pcie-ep@f102000 {

		compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";

		reg = <0x00 0x0f102000 0x00 0x1000>,

		      <0x00 0x0f100000 0x00 0x400>,

		      <0x00 0x0d000000 0x00 0x00800000>,

		      <0x00 0x68000000 0x00 0x08000000>;

		reg-names = "intd_cfg", "user_cfg", "reg", "mem";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;

		ti,syscon-pcie-ctrl = <&main_conf 0x4070>;

		max-link-speed = <2>;

		num-lanes = <1>;

		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 114 0>;

		clock-names = "fck";

		max-functions = /bits/ 8 <1>;

	};

};

arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi

+3 −6
Original line number Diff line number Diff line
@@ -9,8 +9,6 @@ &cbass_mcu { 
	mcu_uart0: serial@4a00000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x04a00000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -22,8 +20,6 @@ mcu_uart0: serial@4a00000 { 
	mcu_uart1: serial@4a10000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x04a10000 0x00 0x100>;

		reg-shift = <2>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <48000000>;

		current-speed = <115200>;
@@ -74,8 +70,9 @@ mcu_spi1: spi@4b10000 { 
		clocks = <&k3_clks 148 0>;

	};



	mcu_gpio_intr: interrupt-controller1 {

	mcu_gpio_intr: interrupt-controller@4210000 {

		compatible = "ti,sci-intr";

		reg = <0x00 0x04210000 0x00 0x200>;

		ti,intr-trigger-type = <1>;

		interrupt-controller;

		interrupt-parent = <&gic500>;
@@ -86,7 +83,7 @@ mcu_gpio_intr: interrupt-controller1 { 
	};



	mcu_gpio0: gpio@4201000 {

		compatible = "ti,am64-gpio", "keystone-gpio";

		compatible = "ti,am64-gpio", "ti,keystone-gpio";

		reg = <0x0 0x4201000 0x0 0x100>;

		gpio-controller;

		#gpio-cells = <2>;

arch/arm64/boot/dts/ti/k3-am642-evm.dts

+109 −1
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 


/dts-v1/;



#include <dt-bindings/phy/phy.h>

#include <dt-bindings/mux/ti-serdes.h>

#include <dt-bindings/leds/common.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/net/ti-dp83867.h>
@@ -36,6 +38,60 @@ secure_ddr: optee@9e800000 { 
			alignment = <0x1000>;

			no-map;

		};



		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa0000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa0100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa1000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa1100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa2000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa2100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa3000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa3100000 0x00 0xf00000>;

			no-map;

		};



		rtos_ipc_memory_region: ipc-memories@a5000000 {

			reg = <0x00 0xa5000000 0x00 0x00800000>;

			alignment = <0x1000>;

			no-map;

		};

	};



	evm_12v0: fixedregulator-evm12v0 {
@@ -334,7 +390,7 @@ &mcu_spi1 { 
&main_spi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_spi0_pins_default>;

	ti,pindir-d0-out-d1-in = <1>;

	ti,pindir-d0-out-d1-in;

	eeprom@0 {

		compatible = "microchip,93lc46b";

		reg = <0>;
@@ -466,3 +522,55 @@ mbox_m4_0: mbox-m4-0 { 
&mailbox0_cluster7 {

	status = "disabled";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

};



&serdes_ln_ctrl {

	idle-states = <AM64_SERDES0_LANE0_PCIE0>;

};



&serdes0 {

	serdes0_pcie_link: phy@0 {

		reg = <0>;

		cdns,num-lanes = <1>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_PCIE>;

		resets = <&serdes_wiz0 1>;

	};

};



&pcie0_rc {

	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <1>;

};



&pcie0_ep {

	phys = <&serdes0_pcie_link>;

	phy-names = "pcie-phy";

	num-lanes = <1>;

	status = "disabled";

};

arch/arm64/boot/dts/ti/k3-am642-sk.dts

+121 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 


/dts-v1/;



#include <dt-bindings/mux/ti-serdes.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/net/ti-dp83867.h>

#include "k3-am642.dtsi"
@@ -35,6 +37,60 @@ secure_ddr: optee@9e800000 { 
			alignment = <0x1000>;

			no-map;

		};



		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa0000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa0100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa1000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa1100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa2000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa2100000 0x00 0xf00000>;

			no-map;

		};



		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa3000000 0x00 0x100000>;

			no-map;

		};



		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {

			compatible = "shared-dma-pool";

			reg = <0x00 0xa3100000 0x00 0xf00000>;

			no-map;

		};



		rtos_ipc_memory_region: ipc-memories@a5000000 {

			reg = <0x00 0xa5000000 0x00 0x00800000>;

			alignment = <0x1000>;

			no-map;

		};

	};



	vusb_main: fixed-regulator-vusb-main5v0 {
@@ -85,6 +141,12 @@ AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ 
		>;

	};



	main_usb0_pins_default: main-usb0-pins-default {

		pinctrl-single,pins = <

			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */

		>;

	};



	main_i2c1_pins_default: main-i2c1-pins-default {

		pinctrl-single,pins = <

			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@@ -235,6 +297,33 @@ &sdhci1 { 
	disable-wp;

};



&serdes_ln_ctrl {

	idle-states = <AM64_SERDES0_LANE0_USB>;

};



&serdes0 {

	serdes0_usb_link: phy@0 {

		reg = <0>;

		cdns,num-lanes = <1>;

		#phy-cells = <0>;

		cdns,phy-type = <PHY_TYPE_USB3>;

		resets = <&serdes_wiz0 1>;

	};

};



&usbss0 {

	ti,vbus-divider;

};



&usb0 {

	dr_mode = "host";

	maximum-speed = "super-speed";

	pinctrl-names = "default";

	pinctrl-0 = <&main_usb0_pins_default>;

	phys = <&serdes0_usb_link>;

	phy-names = "cdns3,usb3-phy";

};



&cpsw3g {

	pinctrl-names = "default";

	pinctrl-0 = <&mdio1_pins_default
@@ -332,3 +421,35 @@ mbox_m4_0: mbox-m4-0 { 
&mailbox0_cluster7 {

	status = "disabled";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

};



&pcie0_rc {

	status = "disabled";

};



&pcie0_ep {

	status = "disabled";

};