Commit 7085e4e2 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v6.8-1' of... 

Merge tag 'intel-pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel

 into devel

intel-pinctrl for v6.8-1

* New agnostic driver to support Lunar Lake and newer platforms
* New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
* Update drivers to use new PM helpers
* Use RAII for locking in a few drivers (Raag, Andy)
* Reduce locking scope in some functions (Raag)
* Miscellaneous cleanups (Raag)

The following is an automated git shortlog grouped by driver:

alderlake:
 -  Switch to use Intel pin control PM ops

baytrail:
 -  Simplify code with cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Factor out byt_gpio_force_input_mode()
 -  Fix types of config value in byt_pin_config_set()

broxton:
 -  Switch to use Intel pin control PM ops

cannonlake:
 -  Switch to use Intel pin control PM ops

cedarfork:
 -  Switch to use Intel pin control PM ops

denverton:
 -  Switch to use Intel pin control PM ops

elkhartlake:
 -  Switch to use Intel pin control PM ops

emmitsburg:
 -  Switch to use Intel pin control PM ops

geminilake:
 -  Switch to use Intel pin control PM ops

icelake:
 -  Switch to use Intel pin control PM ops

intel:
 -  Add Intel Meteor Point pin controller and GPIO support
 -  use the correct _PM_OPS() export macro
 -  Add a generic Intel pin control platform driver
 -  Revert "Unexport intel_pinctrl_probe()"
 -  allow independent COMPILE_TEST
 -  Refactor intel_pinctrl_get_soc_data()
 -  Move default strength assignment to a switch-case
 -  Make PM ops functions static
 -  Provide Intel pin control wide PM ops structure

jasperlake:
 -  Switch to use Intel pin control PM ops

lakefield:
 -  Switch to use Intel pin control PM ops

lewisburg:
 -  Switch to use Intel pin control PM ops

lynxpoint:
 -  Simplify code with cleanup helpers

meteorlake:
 -  Switch to use Intel pin control PM ops

sunrisepoint:
 -  Switch to use Intel pin control PM ops

tangier:
 -  simplify locking using cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Enable 910 Ohm bias

tigerlake:
 -  Switch to use Intel pin control PM ops

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 915fdc94 ebe7f339

drivers/pinctrl/intel/Kconfig

+20 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# Intel pin control drivers

menu "Intel pinctrl drivers"

	depends on ACPI && (X86 || COMPILE_TEST)

	depends on (ACPI && X86) || COMPILE_TEST



config PINCTRL_BAYTRAIL

	bool "Intel Baytrail GPIO pin control"
@@ -37,6 +37,16 @@ config PINCTRL_INTEL 
	select GPIOLIB

	select GPIOLIB_IRQCHIP



config PINCTRL_INTEL_PLATFORM

	tristate "Intel pinctrl and GPIO platform driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  This pinctrl driver provides an interface that allows configuring

	  of Intel PCH pins and using them as GPIOs. Currently the following

	  Intel SoCs / platforms require this to be functional:

	  - Lunar Lake



config PINCTRL_ALDERLAKE

	tristate "Intel Alder Lake pinctrl and GPIO driver"

	select PINCTRL_INTEL
@@ -128,6 +138,15 @@ config PINCTRL_METEORLAKE 
	  This pinctrl driver provides an interface that allows configuring

	  of Intel Meteor Lake pins and using them as GPIOs.



config PINCTRL_METEORPOINT

	tristate "Intel Meteor Point pinctrl and GPIO driver"

	depends on ACPI

	select PINCTRL_INTEL

	help

	  Meteor Point is the PCH of Intel Meteor Lake. This pinctrl driver

	  provides an interface that allows configuring of PCH pins and

	  using them as GPIOs.



config PINCTRL_SUNRISEPOINT

	tristate "Intel Sunrisepoint pinctrl and GPIO driver"

	select PINCTRL_INTEL

drivers/pinctrl/intel/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o 
obj-$(CONFIG_PINCTRL_MERRIFIELD)	+= pinctrl-merrifield.o

obj-$(CONFIG_PINCTRL_MOOREFIELD)	+= pinctrl-moorefield.o

obj-$(CONFIG_PINCTRL_INTEL)		+= pinctrl-intel.o

obj-$(CONFIG_PINCTRL_INTEL_PLATFORM)	+= pinctrl-intel-platform.o

obj-$(CONFIG_PINCTRL_ALDERLAKE)		+= pinctrl-alderlake.o

obj-$(CONFIG_PINCTRL_BROXTON)		+= pinctrl-broxton.o

obj-$(CONFIG_PINCTRL_CANNONLAKE)	+= pinctrl-cannonlake.o
@@ -21,5 +22,6 @@ obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o 
obj-$(CONFIG_PINCTRL_LAKEFIELD)		+= pinctrl-lakefield.o

obj-$(CONFIG_PINCTRL_LEWISBURG)		+= pinctrl-lewisburg.o

obj-$(CONFIG_PINCTRL_METEORLAKE)	+= pinctrl-meteorlake.o

obj-$(CONFIG_PINCTRL_METEORPOINT)	+= pinctrl-meteorpoint.o

obj-$(CONFIG_PINCTRL_SUNRISEPOINT)	+= pinctrl-sunrisepoint.o

obj-$(CONFIG_PINCTRL_TIGERLAKE)		+= pinctrl-tigerlake.o

drivers/pinctrl/intel/pinctrl-alderlake.c

+2 −3
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/mod_devicetable.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm.h>



#include <linux/pinctrl/pinctrl.h>
@@ -733,14 +734,12 @@ static const struct acpi_device_id adl_pinctrl_acpi_match[] = { 
};

MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);



static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops);



static struct platform_driver adl_pinctrl_driver = {

	.probe = intel_pinctrl_probe_by_hid,

	.driver = {

		.name = "alderlake-pinctrl",

		.acpi_match_table = adl_pinctrl_acpi_match,

		.pm = &adl_pinctrl_pm_ops,

		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),

	},

};

module_platform_driver(adl_pinctrl_driver);

drivers/pinctrl/intel/pinctrl-baytrail.c

+91 −138
Original line number Diff line number Diff line
@@ -588,10 +588,9 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 
				     const struct intel_pingroup group,

				     unsigned int func)

{

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	for (i = 0; i < group.grp.npins; i++) {

		void __iomem *padcfg0;
@@ -609,18 +608,15 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 
		value |= func;

		writel(value, padcfg0);

	}



	raw_spin_unlock_irqrestore(&byt_lock, flags);

}



static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,

				    const struct intel_pingroup group,

				    const unsigned int *func)

{

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	for (i = 0; i < group.grp.npins; i++) {

		void __iomem *padcfg0;
@@ -638,8 +634,6 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 
		value |= func[i];

		writel(value, padcfg0);

	}



	raw_spin_unlock_irqrestore(&byt_lock, flags);

}



static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
@@ -677,10 +671,10 @@ static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 
static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)

{

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);

	unsigned long flags;

	u32 value;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	value = readl(reg);



	/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
@@ -688,7 +682,6 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off 
		value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);



	writel(value, reg);

	raw_spin_unlock_irqrestore(&byt_lock, flags);

}



static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
@@ -698,9 +691,8 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 
	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);

	u32 value, gpio_mux;

	unsigned long flags;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	/*

	 * In most cases, func pin mux 000 means GPIO function.
@@ -713,15 +705,14 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 
	 */

	value = readl(reg) & BYT_PIN_MUX;

	gpio_mux = byt_get_gpio_mux(vg, offset);

	if (gpio_mux != value) {

	if (gpio_mux == value)

		return 0;



	value = readl(reg) & ~BYT_PIN_MUX;

	value |= gpio_mux;

	writel(value, reg);



	dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);

	}



	raw_spin_unlock_irqrestore(&byt_lock, flags);



	return 0;

}
@@ -759,10 +750,9 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 
{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	u32 value;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	value = readl(val_reg);

	value &= ~BYT_DIR_MASK;
@@ -773,8 +763,6 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 


	writel(value, val_reg);



	raw_spin_unlock_irqrestore(&byt_lock, flags);



	return 0;

}
@@ -811,6 +799,7 @@ static int byt_set_pull_strength(u32 *reg, u16 strength) 
	*reg &= ~BYT_PULL_STR_MASK;



	switch (strength) {

	case 1: /* Set default strength value in case none is given */

	case 2000:

		*reg |= BYT_PULL_STR_2K;

		break;
@@ -830,6 +819,24 @@ static int byt_set_pull_strength(u32 *reg, u16 strength) 
	return 0;

}



static void byt_gpio_force_input_mode(struct intel_pinctrl *vg, unsigned int offset)

{

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	u32 value;



	value = readl(reg);

	if (!(value & BYT_INPUT_EN))

		return;



	/*

	 * Pull assignment is only applicable in input mode. If

	 * chip is not in input mode, set it and warn about it.

	 */

	value &= ~BYT_INPUT_EN;

	writel(value, reg);

	dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);

}



static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,

			      unsigned long *config)

{
@@ -838,15 +845,15 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 
	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);

	unsigned long flags;

	u32 conf, pull, val, debounce;

	u16 arg = 0;



	raw_spin_lock_irqsave(&byt_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &byt_lock) {

		conf = readl(conf_reg);

	pull = conf & BYT_PULL_ASSIGN_MASK;

		val = readl(val_reg);

	raw_spin_unlock_irqrestore(&byt_lock, flags);

	}



	pull = conf & BYT_PULL_ASSIGN_MASK;



	switch (param) {

	case PIN_CONFIG_BIAS_DISABLE:
@@ -873,9 +880,8 @@ static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 
		if (!(conf & BYT_DEBOUNCE_EN))

			return -EINVAL;



		raw_spin_lock_irqsave(&byt_lock, flags);

		scoped_guard(raw_spinlock_irqsave, &byt_lock)

			debounce = readl(db_reg);

		raw_spin_unlock_irqrestore(&byt_lock, flags);



		switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {

		case BYT_DEBOUNCE_PULSE_375US:
@@ -919,18 +925,16 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 
			      unsigned int num_configs)

{

	struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);

	unsigned int param, arg;

	void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);

	u32 conf, val, db_pulse, debounce;

	unsigned long flags;

	int i, ret = 0;

	u32 conf, db_pulse, debounce;

	enum pin_config_param param;

	int i, ret;

	u32 arg;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	conf = readl(conf_reg);

	val = readl(val_reg);



	for (i = 0; i < num_configs; i++) {

		param = pinconf_to_config_param(configs[i]);
@@ -941,59 +945,30 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 
			conf &= ~BYT_PULL_ASSIGN_MASK;

			break;

		case PIN_CONFIG_BIAS_PULL_DOWN:

			/* Set default strength value in case none is given */

			if (arg == 1)

				arg = 2000;



			/*

			 * Pull assignment is only applicable in input mode. If

			 * chip is not in input mode, set it and warn about it.

			 */

			if (val & BYT_INPUT_EN) {

				val &= ~BYT_INPUT_EN;

				writel(val, val_reg);

				dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);

			}

			byt_gpio_force_input_mode(vg, offset);



			conf &= ~BYT_PULL_ASSIGN_MASK;

			conf |= BYT_PULL_ASSIGN_DOWN;

			ret = byt_set_pull_strength(&conf, arg);

			if (ret)

				return ret;



			break;

		case PIN_CONFIG_BIAS_PULL_UP:

			/* Set default strength value in case none is given */

			if (arg == 1)

				arg = 2000;



			/*

			 * Pull assignment is only applicable in input mode. If

			 * chip is not in input mode, set it and warn about it.

			 */

			if (val & BYT_INPUT_EN) {

				val &= ~BYT_INPUT_EN;

				writel(val, val_reg);

				dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);

			}

			byt_gpio_force_input_mode(vg, offset);



			conf &= ~BYT_PULL_ASSIGN_MASK;

			conf |= BYT_PULL_ASSIGN_UP;

			ret = byt_set_pull_strength(&conf, arg);

			if (ret)

				return ret;



			break;

		case PIN_CONFIG_INPUT_DEBOUNCE:

			if (arg) {

				conf |= BYT_DEBOUNCE_EN;

			} else {

				conf &= ~BYT_DEBOUNCE_EN;



				/*

				 * No need to update the pulse value.

				 * Debounce is going to be disabled.

				 */

				break;

			}



			switch (arg) {

			case 0:

				db_pulse = 0;

				break;

			case 375:

				db_pulse = BYT_DEBOUNCE_PULSE_375US;

				break;
@@ -1016,33 +991,28 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 
				db_pulse = BYT_DEBOUNCE_PULSE_24MS;

				break;

			default:

				if (arg)

					ret = -EINVAL;

				break;

				return -EINVAL;

			}



			if (ret)

				break;



			if (db_pulse) {

				debounce = readl(db_reg);

				debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;

				writel(debounce, db_reg);



			break;

		default:

			ret = -ENOTSUPP;

				conf |= BYT_DEBOUNCE_EN;

			} else {

				conf &= ~BYT_DEBOUNCE_EN;

			}



		if (ret)

			break;

		default:

			return -ENOTSUPP;

		}

	}



	if (!ret)

	writel(conf, conf_reg);



	raw_spin_unlock_irqrestore(&byt_lock, flags);



	return ret;

	return 0;

}



static const struct pinconf_ops byt_pinconf_ops = {
@@ -1062,12 +1032,10 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 
{

	struct intel_pinctrl *vg = gpiochip_get_data(chip);

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	u32 val;



	raw_spin_lock_irqsave(&byt_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &byt_lock)

		val = readl(reg);

	raw_spin_unlock_irqrestore(&byt_lock, flags);



	return !!(val & BYT_LEVEL);

}
@@ -1075,35 +1043,34 @@ static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 
static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)

{

	struct intel_pinctrl *vg = gpiochip_get_data(chip);

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	void __iomem *reg;

	u32 old_val;



	reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	if (!reg)

		return;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	old_val = readl(reg);

	if (value)

		writel(old_val | BYT_LEVEL, reg);

	else

		writel(old_val & ~BYT_LEVEL, reg);

	raw_spin_unlock_irqrestore(&byt_lock, flags);

}



static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)

{

	struct intel_pinctrl *vg = gpiochip_get_data(chip);

	void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	void __iomem *reg;

	u32 value;



	reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	if (!reg)

		return -EINVAL;



	raw_spin_lock_irqsave(&byt_lock, flags);

	scoped_guard(raw_spinlock_irqsave, &byt_lock)

		value = readl(reg);

	raw_spin_unlock_irqrestore(&byt_lock, flags);



	if (!(value & BYT_OUTPUT_EN))

		return GPIO_LINE_DIRECTION_OUT;
@@ -1117,17 +1084,15 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 
{

	struct intel_pinctrl *vg = gpiochip_get_data(chip);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	u32 reg;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	reg = readl(val_reg);

	reg &= ~BYT_DIR_MASK;

	reg |= BYT_OUTPUT_EN;

	writel(reg, val_reg);



	raw_spin_unlock_irqrestore(&byt_lock, flags);

	return 0;

}
@@ -1142,10 +1107,9 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, 
{

	struct intel_pinctrl *vg = gpiochip_get_data(chip);

	void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);

	unsigned long flags;

	u32 reg;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	byt_gpio_direct_irq_check(vg, offset);
@@ -1158,7 +1122,6 @@ static int byt_gpio_direction_output(struct gpio_chip *chip, 


	writel(reg, val_reg);



	raw_spin_unlock_irqrestore(&byt_lock, flags);

	return 0;

}
@@ -1173,7 +1136,6 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 
		void __iomem *conf_reg, *val_reg;

		const char *pull_str = NULL;

		const char *pull = NULL;

		unsigned long flags;

		unsigned int pin;



		pin = vg->soc->pins[i].number;
@@ -1190,10 +1152,10 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 
			continue;

		}



		raw_spin_lock_irqsave(&byt_lock, flags);

		scoped_guard(raw_spinlock_irqsave, &byt_lock) {

			conf0 = readl(conf_reg);

			val = readl(val_reg);

		raw_spin_unlock_irqrestore(&byt_lock, flags);

		}



		comm = intel_get_community(vg, pin);

		if (!comm) {
@@ -1278,9 +1240,9 @@ static void byt_irq_ack(struct irq_data *d) 
	if (!reg)

		return;



	raw_spin_lock(&byt_lock);

	guard(raw_spinlock)(&byt_lock);



	writel(BIT(hwirq % 32), reg);

	raw_spin_unlock(&byt_lock);

}



static void byt_irq_mask(struct irq_data *d)
@@ -1298,7 +1260,6 @@ static void byt_irq_unmask(struct irq_data *d) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct intel_pinctrl *vg = gpiochip_get_data(gc);

	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	unsigned long flags;

	void __iomem *reg;

	u32 value;
@@ -1308,7 +1269,8 @@ static void byt_irq_unmask(struct irq_data *d) 
	if (!reg)

		return;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	value = readl(reg);



	switch (irqd_get_trigger_type(d)) {
@@ -1330,23 +1292,21 @@ static void byt_irq_unmask(struct irq_data *d) 
	}



	writel(value, reg);



	raw_spin_unlock_irqrestore(&byt_lock, flags);

}



static int byt_irq_type(struct irq_data *d, unsigned int type)

{

	struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));

	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	u32 value;

	unsigned long flags;

	void __iomem *reg;

	u32 value;



	reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);

	if (!reg)

		return -EINVAL;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	value = readl(reg);



	WARN(value & BYT_DIRECT_IRQ_EN,
@@ -1368,8 +1328,6 @@ static int byt_irq_type(struct irq_data *d, unsigned int type) 
	else if (type & IRQ_TYPE_LEVEL_MASK)

		irq_set_handler_locked(d, handle_level_irq);



	raw_spin_unlock_irqrestore(&byt_lock, flags);



	return 0;

}
@@ -1401,9 +1359,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) 
			continue;

		}



		raw_spin_lock(&byt_lock);

		scoped_guard(raw_spinlock, &byt_lock)

			pending = readl(reg);

		raw_spin_unlock(&byt_lock);

		for_each_set_bit(pin, &pending, 32)

			generic_handle_domain_irq(vg->chip.irq.domain, base + pin);

	}
@@ -1666,10 +1623,9 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 
static int byt_gpio_suspend(struct device *dev)

{

	struct intel_pinctrl *vg = dev_get_drvdata(dev);

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	for (i = 0; i < vg->soc->npins; i++) {

		void __iomem *reg;
@@ -1693,17 +1649,15 @@ static int byt_gpio_suspend(struct device *dev) 
		vg->context.pads[i].val = value;

	}



	raw_spin_unlock_irqrestore(&byt_lock, flags);

	return 0;

}



static int byt_gpio_resume(struct device *dev)

{

	struct intel_pinctrl *vg = dev_get_drvdata(dev);

	unsigned long flags;

	int i;



	raw_spin_lock_irqsave(&byt_lock, flags);

	guard(raw_spinlock_irqsave)(&byt_lock);



	for (i = 0; i < vg->soc->npins; i++) {

		void __iomem *reg;
@@ -1743,7 +1697,6 @@ static int byt_gpio_resume(struct device *dev) 
		}

	}



	raw_spin_unlock_irqrestore(&byt_lock, flags);

	return 0;

}

drivers/pinctrl/intel/pinctrl-broxton.c

+2 −3
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/mod_devicetable.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pm.h>



#include <linux/pinctrl/pinctrl.h>
@@ -1000,14 +1001,12 @@ static const struct platform_device_id bxt_pinctrl_platform_ids[] = { 
};

MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids);



static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);



static struct platform_driver bxt_pinctrl_driver = {

	.probe = intel_pinctrl_probe_by_uid,

	.driver = {

		.name = "broxton-pinctrl",

		.acpi_match_table = bxt_pinctrl_acpi_match,

		.pm = &bxt_pinctrl_pm_ops,

		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),

	},

	.id_table = bxt_pinctrl_platform_ids,

};