Commit 70892277 authored by Connor Abbott's avatar Connor Abbott Committed by Will Deacon
Browse files

iommu/arm-smmu-qcom: Make set_stall work when the device is on 



Up until now we have only called the set_stall callback during
initialization when the device is off. But we will soon start calling it
to temporarily disable stall-on-fault when the device is on, so handle
that by checking if the device is on and writing SCTLR.

Signed-off-by: default avatarConnor Abbott <cwabbott0@gmail.com>
Reviewed-by: default avatarRob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20250520-msm-gpu-fault-fixes-next-v8-3-fce6ee218787@gmail.com


[will: Fix "mixed declarations and code" warning from sparse]
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 3053a2c5

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

+30 −3
Original line number Diff line number Diff line
@@ -112,12 +112,39 @@ static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled) 
{

	struct arm_smmu_domain *smmu_domain = (void *)cookie;

	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;

	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);

	u32 mask = BIT(cfg->cbndx);

	bool stall_changed = !!(qsmmu->stall_enabled & mask) != enabled;

	unsigned long flags;



	if (enabled)

		qsmmu->stall_enabled |= BIT(cfg->cbndx);

		qsmmu->stall_enabled |= mask;

	else

		qsmmu->stall_enabled &= ~BIT(cfg->cbndx);

		qsmmu->stall_enabled &= ~mask;



	/*

	 * If the device is on and we changed the setting, update the register.

	 * The spec pseudocode says that CFCFG is resampled after a fault, and

	 * we believe that no implementations cache it in the TLB, so it should

	 * be safe to change it without a TLB invalidation.

	 */

	if (stall_changed && pm_runtime_get_if_active(smmu->dev) > 0) {

		u32 reg;



		spin_lock_irqsave(&smmu_domain->cb_lock, flags);

		reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR);



		if (enabled)

			reg |= ARM_SMMU_SCTLR_CFCFG;

		else

			reg &= ~ARM_SMMU_SCTLR_CFCFG;



		arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR, reg);

		spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);



		pm_runtime_put_autosuspend(smmu->dev);

	}

}



static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set)

include/linux/adreno-smmu-priv.h

+3 −3
Original line number Diff line number Diff line
@@ -45,9 +45,9 @@ struct adreno_smmu_fault_info { 
 *                 TTBR0 translation is enabled with the specified cfg

 * @get_fault_info: Called by the GPU fault handler to get information about

 *                  the fault

 * @set_stall:     Configure whether stall on fault (CFCFG) is enabled.  Call

 *                 before set_ttbr0_cfg().  If stalling on fault is enabled,

 *                 the GPU driver must call resume_translation()

 * @set_stall:     Configure whether stall on fault (CFCFG) is enabled. If

 *                 stalling on fault is enabled, the GPU driver must call

 *                 resume_translation()

 * @resume_translation: Resume translation after a fault

 *

 * @set_prr_bit:   [optional] Configure the GPU's Partially Resident