Commit 708e8af4 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Mathieu Poirier
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arm64: errata: Add detection for TRBE trace data corruption 



TRBE implementations affected by Arm erratum #1902691 might corrupt trace
data or deadlock, when it's being written into the memory. So effectively
TRBE is broken and hence cannot be used to capture trace data. This adds
a new errata ARM64_ERRATUM_1902691 in arm64 errata framework.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1643120437-14352-5-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent 3bd94a87

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2038923        | ARM64_ERRATUM_2038923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #1902691        | ARM64_ERRATUM_1902691       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

arch/arm64/Kconfig

+18 −0
Original line number Diff line number Diff line
@@ -819,6 +819,24 @@ config ARM64_ERRATUM_2038923 


	  If unsure, say Y.



config ARM64_ERRATUM_1902691

	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.



	  Affected Cortex-A510 core might cause trace data corruption, when being written

	  into the memory. Effectively TRBE is broken and hence cannot be used to capture

	  trace data.



	  Work around this problem in the driver by just preventing TRBE initialization on

	  affected cpus. The firmware must have disabled the access to TRBE for the kernel

	  on such implementations. This will cover the kernel for any firmware that doesn't

	  do this already.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/kernel/cpu_errata.c

+9 −0
Original line number Diff line number Diff line
@@ -615,6 +615,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		/* Cortex-A510 r0p0 - r0p2 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1902691

	{

		.desc = "ARM erratum 1902691",

		.capability = ARM64_WORKAROUND_1902691,



		/* Cortex-A510 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)

	},

#endif

	{

	}

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ WORKAROUND_1508412 
WORKAROUND_1542419

WORKAROUND_2064142

WORKAROUND_2038923

WORKAROUND_1902691

WORKAROUND_TRBE_OVERWRITE_FILL_MODE

WORKAROUND_TSB_FLUSH_FAILURE

WORKAROUND_TRBE_WRITE_OUT_OF_RANGE