Commit 70a114da authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Heiko Stuebner
Browse files

clk: rockchip: introduce auxiliary GRFs 



The MUXGRF clock branch type depends on having access to some sort of
GRF as a regmap to be registered. So far, we could easily get away with
only ever having one GRF stowed away in the context.

However, newer Rockchip SoCs, such as the RK3576, have several GRFs
which are relevant for clock purposes. It already depends on the pmu0
GRF for MUXGRF reasons, but could get away with not refactoring this
because it didn't need the sysgrf at all, so could overwrite the pointer
in the clock provider to the pmu0 grf regmap handle.

In preparation for needing to finally access more than one GRF per SoC,
let's untangle this. Introduce an auxiliary GRF hashmap, and a GRF type
enum. The hashmap is keyed by the enum, and clock branches now have a
struct member to store the value of that enum, which defaults to the
system GRF.

The SoC-specific _clk_init function can then insert pointers to GRF
regmaps into the hashmap based on the grf type.

During clock branch registration, we then pick the right GRF for each
branch from the hashmap if something other than the sys GRF is
requested.

The reason for doing it with this grf type indirection in the clock
branches is so that we don't need to define the MUXGRF branches in a
separate step, just to have a direct pointer to a regmap available
already.

Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-2-376cef19dd7c@collabora.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 6657acc8

drivers/clk/rockchip/clk-rk3288.c

+1 −1
Original line number Diff line number Diff line
@@ -418,7 +418,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
			RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,

			RK3288_CLKGATE_CON(3), 11, GFLAGS),

	MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,

			RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),

			RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS, grf_type_sys),

	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,

		RK3288_CLKGATE_CON(9), 0, GFLAGS),

drivers/clk/rockchip/clk-rk3328.c

+3 −3
Original line number Diff line number Diff line
@@ -677,9 +677,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,

			RK3328_CLKGATE_CON(3), 5, GFLAGS),

	MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),

			RK3328_GRF_MAC_CON1, 10, 1, MFLAGS, grf_type_sys),

	MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),

			RK3328_GRF_SOC_CON4, 14, 1, MFLAGS, grf_type_sys),



	COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,

			RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -692,7 +692,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,

			RK3328_CLKGATE_CON(9), 2, GFLAGS),

	MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,

			RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),

			RK3328_GRF_MAC_CON2, 10, 1, MFLAGS, grf_type_sys),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),

drivers/clk/rockchip/clk-rk3568.c

+1 −1
Original line number Diff line number Diff line
@@ -591,7 +591,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 
			RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3568_CLKGATE_CON(4), 0, GFLAGS),

	MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,

			RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),

			RK3568_CLKSEL_CON(9), 15, 1, MFLAGS, grf_type_sys),



	COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,

			RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,

drivers/clk/rockchip/clk-rk3576.c

+22 −10
Original line number Diff line number Diff line
@@ -1676,13 +1676,13 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { 


	/* phy ref */

	MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p,  0,

			RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS),

			RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS, grf_type_pmu0),

	MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p,  0,

			RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS),

			RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS, grf_type_pmu0),

	MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p,  0,

			RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS),

			RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS, grf_type_pmu0),

	MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p,  0,

			RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS),

			RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS, grf_type_pmu0),



	/* secure ns */

	COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL,
@@ -1725,13 +1725,14 @@ static void __init rk3576_clk_init(struct device_node *np) 
	struct rockchip_clk_provider *ctx;

	unsigned long clk_nr_clks;

	void __iomem *reg_base;

	struct regmap *grf;

	struct rockchip_aux_grf *pmu0_grf_e;

	struct regmap *pmu0_grf;



	clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,

					ARRAY_SIZE(rk3576_clk_branches)) + 1;



	grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");

	if (IS_ERR(grf)) {

	pmu0_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");

	if (IS_ERR(pmu0_grf)) {

		pr_err("%s: could not get PMU0 GRF syscon\n", __func__);

		return;

	}
@@ -1745,11 +1746,16 @@ static void __init rk3576_clk_init(struct device_node *np) 
	ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);

	if (IS_ERR(ctx)) {

		pr_err("%s: rockchip clk init failed\n", __func__);

		iounmap(reg_base);

		return;

		goto err_unmap;

	}



	ctx->grf = grf;

	pmu0_grf_e = kzalloc(sizeof(*pmu0_grf_e), GFP_KERNEL);

	if (!pmu0_grf_e)

		goto err_unmap;



	pmu0_grf_e->grf = pmu0_grf;

	pmu0_grf_e->type = grf_type_pmu0;

	hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0);



	rockchip_clk_register_plls(ctx, rk3576_pll_clks,

				   ARRAY_SIZE(rk3576_pll_clks),
@@ -1772,6 +1778,12 @@ static void __init rk3576_clk_init(struct device_node *np) 
	rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL);



	rockchip_clk_of_add_provider(np, ctx);



	return;



err_unmap:

	iounmap(reg_base);

	return;

}



CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init);

drivers/clk/rockchip/clk-rv1126.c

+1 −1
Original line number Diff line number Diff line
@@ -857,7 +857,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { 
			RV1126_GMAC_CON, 5, 1, MFLAGS),

	MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |

			CLK_SET_RATE_NO_REPARENT,

			RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),

			RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS, grf_type_sys),



	GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,

			RV1126_CLKGATE_CON(20), 7, GFLAGS),