Unverified Commit 70a57b24 authored by Miguel Ojeda's avatar Miguel Ojeda Committed by Palmer Dabbelt
Browse files

RISC-V: enable building 64-bit kernels with rust support 



The rust modules work on 64-bit RISC-V, with no twiddling required.
Select HAVE_RUST and provide the required flags to kbuild so that the
modules can be used. The Makefile and Kconfig changes are lifted from
work done by Miguel in the Rust-for-Linux tree, hence his authorship.
Following the rabbit hole, the Makefile changes originated in a script,
created based on config files originally added by Gary, hence his
co-authorship.

32-bit is broken in core rust code, so support is limited to 64-bit:
ld.lld: error: undefined symbol: __udivdi3

As 64-bit RISC-V is now supported, add it to the arch support table.

Co-developed-by: default avatarGary Guo <gary@garyguo.net>
Signed-off-by: default avatarGary Guo <gary@garyguo.net>
Signed-off-by: default avatarMiguel Ojeda <ojeda@kernel.org>
Co-developed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240409-silencer-book-ce1320f06aab@spud


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 300ce44c

Documentation/rust/arch-support.rst

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ Architecture Level of support Constraints 
=============  ================  ==============================================

``arm64``      Maintained        Little Endian only.

``loongarch``  Maintained        -

``riscv``      Maintained        ``riscv64`` only.

``um``         Maintained        ``x86_64`` only.

``x86``        Maintained        ``x86_64`` only.

=============  ================  ==============================================

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ config RISCV 
	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_RETHOOK if !XIP_KERNEL

	select HAVE_RSEQ

	select HAVE_RUST if 64BIT

	select HAVE_SAMPLE_FTRACE_DIRECT

	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI

	select HAVE_STACKPROTECTOR

arch/riscv/Makefile

+7 −0
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ ifeq ($(CONFIG_ARCH_RV64I),y) 
	KBUILD_AFLAGS += -mabi=lp64



	KBUILD_LDFLAGS += -melf64lriscv



	KBUILD_RUSTFLAGS += -Ctarget-cpu=generic-rv64 --target=riscv64imac-unknown-none-elf \

			    -Cno-redzone

else

	BITS := 32

	UTS_MACHINE := riscv32
@@ -68,6 +71,10 @@ riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd 
riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c

riscv-march-$(CONFIG_RISCV_ISA_V)	:= $(riscv-march-y)v



ifneq ($(CONFIG_RISCV_ISA_C),y)

	KBUILD_RUSTFLAGS += -Ctarget-feature=-c

endif



ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC

KBUILD_CFLAGS += -Wa,-misa-spec=2.2

KBUILD_AFLAGS += -Wa,-misa-spec=2.2

scripts/generate_rust_target.rs

+6 −0
Original line number Diff line number Diff line
@@ -150,6 +150,12 @@ fn main() { 
    // `llvm-target`s are taken from `scripts/Makefile.clang`.

    if cfg.has("ARM64") {

        panic!("arm64 uses the builtin rustc aarch64-unknown-none target");

    } else if cfg.has("RISCV") {

        if cfg.has("64BIT") {

            panic!("64-bit RISC-V uses the builtin rustc riscv64-unknown-none-elf target");

        } else {

            panic!("32-bit RISC-V is an unsupported architecture");

        }

    } else if cfg.has("X86_64") {

        ts.push("arch", "x86_64");

        ts.push(