Commit 70e0af37 authored by Abel Vesa's avatar Abel Vesa Committed by Vinod Koul
Browse files

phy: qcom: qmp-pcie: Add QMP v6 registers layout 



For consistency, add the QMP v6 registers layout even though
they are the same as v5. Also switch all QMP v6 PHYs to use this
new layout.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-2-223c0556908a@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e94b29f2

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+10 −3
Original line number Diff line number Diff line
@@ -116,6 +116,13 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_POWER_DOWN_CONTROL,

};



static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= QPHY_V6_PCS_SW_RESET,

	[QPHY_START_CTRL]		= QPHY_V6_PCS_START_CONTROL,

	[QPHY_PCS_STATUS]		= QPHY_V6_PCS_PCS_STATUS1,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_POWER_DOWN_CONTROL,

};



static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2936,7 +2943,7 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 
	.num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list              = qmp_phy_vreg_l,

	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),

	.regs                   = pciephy_v5_regs_layout,

	.regs                   = pciephy_v6_regs_layout,



	.pwrdn_ctrl             = SW_PWRDN,

	.phy_status             = PHYSTATUS_4_20,
@@ -3069,7 +3076,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 
	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= sm8550_qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

	.regs			= pciephy_v5_regs_layout,

	.regs			= pciephy_v6_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,
@@ -3099,7 +3106,7 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 
	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),

	.vreg_list		= sm8550_qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),

	.regs			= pciephy_v5_regs_layout,

	.regs			= pciephy_v6_regs_layout,



	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,

	.phy_status		= PHYSTATUS_4_20,