Commit 710aebda authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'hisilicon-hns-deadcoding' 

Dr. David Alan Gilbert says:

====================
hisilicon hns deadcoding

From: "Dr. David Alan Gilbert" <linux@treblig.org>

A small set of deadcoding for functions that are not
called, and a couple of function pointers that they
called.

Build tested only; I don't have the hardware.
====================

Link: https://patch.msgid.link/20241218163341.40297-1-linux@treblig.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents b73e56f1 8973ce18

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

+0 −109
Original line number Diff line number Diff line
@@ -3019,115 +3019,6 @@ static struct platform_driver g_dsaf_driver = { 


module_platform_driver(g_dsaf_driver);



/**

 * hns_dsaf_roce_reset - reset dsaf and roce

 * @dsaf_fwnode: Pointer to framework node for the dasf

 * @dereset: false - request reset , true - drop reset

 * return 0 - success , negative -fail

 */

int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)

{

	struct dsaf_device *dsaf_dev;

	struct platform_device *pdev;

	u32 mp;

	u32 sl;

	u32 credit;

	int i;

	static const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {

		{DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},

		{DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},

		{DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},

		{DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},

		{DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},

		{DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},

		{DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},

		{DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},

	};

	static const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},

		{DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},

		{DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},

		{DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},

	};



	/* find the platform device corresponding to fwnode */

	if (is_of_node(dsaf_fwnode)) {

		pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));

	} else if (is_acpi_device_node(dsaf_fwnode)) {

		pdev = hns_dsaf_find_platform_device(dsaf_fwnode);

	} else {

		pr_err("fwnode is neither OF or ACPI type\n");

		return -EINVAL;

	}



	/* check if we were a success in fetching pdev */

	if (!pdev) {

		pr_err("couldn't find platform device for node\n");

		return -ENODEV;

	}



	/* retrieve the dsaf_device from the driver data */

	dsaf_dev = dev_get_drvdata(&pdev->dev);

	if (!dsaf_dev) {

		dev_err(&pdev->dev, "dsaf_dev is NULL\n");

		put_device(&pdev->dev);

		return -ENODEV;

	}



	/* now, make sure we are running on compatible SoC */

	if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {

		dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",

			dsaf_dev->ae_dev.name);

		put_device(&pdev->dev);

		return -ENODEV;

	}



	/* do reset or de-reset according to the flag */

	if (!dereset) {

		/* reset rocee-channels in dsaf and rocee */

		dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,

						      false);

		dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);

	} else {

		/* configure dsaf tx roce correspond to port map and sl map */

		mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);

		for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)

			dsaf_set_field(mp, 7 << i * 3, i * 3,

				       port_map[i][DSAF_ROCE_6PORT_MODE]);

		dsaf_set_field(mp, 3 << i * 3, i * 3, 0);

		dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);



		sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);

		for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)

			dsaf_set_field(sl, 3 << i * 2, i * 2,

				       sl_map[i][DSAF_ROCE_6PORT_MODE]);

		dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);



		/* de-reset rocee-channels in dsaf and rocee */

		dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,

						      true);

		msleep(SRST_TIME_INTERVAL);

		dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);



		/* enable dsaf channel rocee credit */

		credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);

		dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);

		dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);



		dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);

		dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);

	}



	put_device(&pdev->dev);



	return 0;

}

EXPORT_SYMBOL(hns_dsaf_roce_reset);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Huawei Tech. Co., Ltd.");

MODULE_DESCRIPTION("HNS DSAF driver");

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

+0 −28
Original line number Diff line number Diff line
@@ -42,29 +42,6 @@ struct hns_mac_cb; 


#define HNS_MAX_WAIT_CNT 10000



enum dsaf_roce_port_mode {

	DSAF_ROCE_6PORT_MODE,

	DSAF_ROCE_4PORT_MODE,

	DSAF_ROCE_2PORT_MODE,

	DSAF_ROCE_CHAN_MODE_NUM,

};



enum dsaf_roce_port_num {

	DSAF_ROCE_PORT_0,

	DSAF_ROCE_PORT_1,

	DSAF_ROCE_PORT_2,

	DSAF_ROCE_PORT_3,

	DSAF_ROCE_PORT_4,

	DSAF_ROCE_PORT_5,

};



enum dsaf_roce_qos_sl {

	DSAF_ROCE_SL_0,

	DSAF_ROCE_SL_1,

	DSAF_ROCE_SL_2,

	DSAF_ROCE_SL_3,

};



#define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))

#define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP)
@@ -307,9 +284,6 @@ struct dsaf_misc_op { 
	void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);

	void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);

	void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);

	void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,

				   bool dereset);

	void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);



	phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);

	int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
@@ -463,6 +437,4 @@ int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, 
			     u8 mac_id, u8 port_num);

int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port);



int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);



#endif /* __HNS_DSAF_MAIN_H__ */

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

+0 −67
Original line number Diff line number Diff line
@@ -326,69 +326,6 @@ static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, 
				   HNS_XGE_RESET_FUNC, port, dereset);

}



/**

 * hns_dsaf_srst_chns - reset dsaf channels

 * @dsaf_dev: dsaf device struct pointer

 * @msk: xbar channels mask value:

 * @dereset: false - request reset , true - drop reset

 *

 * bit0-5 for xge0-5

 * bit6-11 for ppe0-5

 * bit12-17 for roce0-5

 * bit18-19 for com/dfx

 */

static void

hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)

{

	u32 reg_addr;



	if (!dereset)

		reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;

	else

		reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;



	dsaf_write_sub(dsaf_dev, reg_addr, msk);

}



/**

 * hns_dsaf_srst_chns_acpi - reset dsaf channels

 * @dsaf_dev: dsaf device struct pointer

 * @msk: xbar channels mask value:

 * @dereset: false - request reset , true - drop reset

 *

 * bit0-5 for xge0-5

 * bit6-11 for ppe0-5

 * bit12-17 for roce0-5

 * bit18-19 for com/dfx

 */

static void

hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)

{

	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,

				   HNS_DSAF_CHN_RESET_FUNC,

				   msk, dereset);

}



static void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset)

{

	if (!dereset) {

		dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);

	} else {

		dsaf_write_sub(dsaf_dev,

			       DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);

		dsaf_write_sub(dsaf_dev,

			       DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);

		msleep(20);

		dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);

	}

}



static void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset)

{

	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,

				   HNS_ROCE_RESET_FUNC, 0, dereset);

}



static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,

				     bool dereset)

{
@@ -729,8 +666,6 @@ struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev) 
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port;

		misc_op->ppe_srst = hns_ppe_srst_by_port;

		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns;

		misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst;



		misc_op->get_phy_if = hns_mac_get_phy_if;

		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
@@ -746,8 +681,6 @@ struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev) 
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;

		misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;

		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi;

		misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi;



		misc_op->get_phy_if = hns_mac_get_phy_if_acpi;

		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt_acpi;

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

+0 −5
Original line number Diff line number Diff line
@@ -195,11 +195,6 @@ void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val) 
	dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);

}



void hns_rcb_start(struct hnae_queue *q, u32 val)

{

	hns_rcb_ring_enable_hw(q, val);

}



/**

 *hns_rcb_common_init_commit_hw - make rcb common init completed

 *@rcb_common: rcb common device

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h

+0 −1
Original line number Diff line number Diff line
@@ -116,7 +116,6 @@ int hns_rcb_buf_size2type(u32 buf_size); 
int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index);

void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index);

int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common);

void hns_rcb_start(struct hnae_queue *q, u32 val);

int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common);

void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode,

			    u16 *max_vfn, u16 *max_q_per_vf);