Commit 710d9cae authored by Yifan Zhang's avatar Yifan Zhang Committed by Alex Deucher
Browse files

drm/amd/pm: drop most smu_cmn_get_smc_version in smu 



smu_check_fw_version is called in smu hw init, thus smu if version
and version are garenteed to be stored in smu context. No need to
call smu_cmn_get_smc_version again after system boot up.

Signed-off-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce6eb957

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+12 −59
Original line number Diff line number Diff line
@@ -963,17 +963,10 @@ static int arcturus_force_clk_levels(struct smu_context *smu, 
	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;

	struct smu_11_0_dpm_table *single_dpm_table = NULL;

	uint32_t soft_min_level, soft_max_level;

	uint32_t smu_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(smu->adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	if ((smu_version >= 0x361200) &&

	    (smu_version <= 0x361a00)) {

	if ((smu->smc_fw_version >= 0x361200) &&

	    (smu->smc_fw_version <= 0x361a00)) {

		dev_err(smu->adev->dev, "Forcing clock level is not supported with "

		       "54.18 - 54.26(included) SMU firmwares\n");

		return -EOPNOTSUPP;
@@ -1344,16 +1337,11 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
	uint32_t i, size = 0;

	int16_t workload_type = 0;

	int result = 0;

	uint32_t smu_version;



	if (!buf)

		return -EINVAL;



	result = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (result)

		return result;



	if (smu_version >= 0x360d00)

	if (smu->smc_fw_version >= 0x360d00)

		size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",

			title[0], title[1], title[2], title[3], title[4], title[5],

			title[6], title[7], title[8], title[9], title[10]);
@@ -1372,7 +1360,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
		if (workload_type < 0)

			continue;



		if (smu_version >= 0x360d00) {

		if (smu->smc_fw_version >= 0x360d00) {

			result = smu_cmn_update_table(smu,

						  SMU_TABLE_ACTIVITY_MONITOR_COEFF,

						  workload_type,
@@ -1387,7 +1375,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu, 
		size += sysfs_emit_at(buf, size, "%2d %14s%s\n",

			i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");



		if (smu_version >= 0x360d00) {

		if (smu->smc_fw_version >= 0x360d00) {

			size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",

				" ",

				0,
@@ -1429,19 +1417,15 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, 
	int workload_type = 0;

	uint32_t profile_mode = input[size];

	int ret = 0;

	uint32_t smu_version;



	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {

		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);

		return -EINVAL;

	}



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret)

		return ret;



	if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&

	     (smu_version >= 0x360d00)) {

	     (smu->smc_fw_version >= 0x360d00)) {

		ret = smu_cmn_update_table(smu,

				       SMU_TABLE_ACTIVITY_MONITOR_COEFF,

				       WORKLOAD_PPLIB_CUSTOM_BIT,
@@ -1517,15 +1501,6 @@ static int arcturus_set_power_profile_mode(struct smu_context *smu, 
static int arcturus_set_performance_level(struct smu_context *smu,

					  enum amd_dpm_forced_level level)

{

	uint32_t smu_version;

	int ret;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(smu->adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	switch (level) {

	case AMD_DPM_FORCED_LEVEL_HIGH:

	case AMD_DPM_FORCED_LEVEL_LOW:
@@ -1533,8 +1508,8 @@ static int arcturus_set_performance_level(struct smu_context *smu, 
	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:

	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:

		if ((smu_version >= 0x361200) &&

		    (smu_version <= 0x361a00)) {

		if ((smu->smc_fw_version >= 0x361200) &&

		    (smu->smc_fw_version <= 0x361a00)) {

			dev_err(smu->adev->dev, "Forcing clock level is not supported with "

			       "54.18 - 54.26(included) SMU firmwares\n");

			return -EOPNOTSUPP;
@@ -2172,16 +2147,11 @@ static void arcturus_i2c_control_fini(struct smu_context *smu) 
static void arcturus_get_unique_id(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t top32 = 0, bottom32 = 0, smu_version;

	uint32_t top32 = 0, bottom32 = 0;

	uint64_t id;



	if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {

		dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");

		return;

	}



	/* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */

	if (smu_version < 0x361700) {

	if (smu->smc_fw_version < 0x361700) {

		dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");

		return;

	}
@@ -2198,8 +2168,6 @@ static int arcturus_set_df_cstate(struct smu_context *smu, 
				  enum pp_df_cstate state)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t smu_version;

	int ret;



	/*

	 * Arcturus does not need the cstate disablement
@@ -2208,14 +2176,8 @@ static int arcturus_set_df_cstate(struct smu_context *smu, 
	if (amdgpu_in_reset(adev) || adev->in_suspend)

		return 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(smu->adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	/* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */

	if (smu_version < 0x360F00) {

	if (smu->smc_fw_version < 0x360F00) {

		dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");

		return -EINVAL;

	}
@@ -2226,17 +2188,8 @@ static int arcturus_set_df_cstate(struct smu_context *smu, 
static int arcturus_select_xgmi_plpd_policy(struct smu_context *smu,

					    enum pp_xgmi_plpd_mode mode)

{

	uint32_t smu_version;

	int ret;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(smu->adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	/* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */

	if (smu_version < 0x00361700) {

	if (smu->smc_fw_version < 0x00361700) {

		dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");

		return -EINVAL;

	}

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+8 −29
Original line number Diff line number Diff line
@@ -907,18 +907,11 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu, 
				       uint32_t *value)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t smu_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {

	case IP_VERSION(11, 0, 9):

		if (smu_version > 0x00341C00)

		if (smu->smc_fw_version > 0x00341C00)

			ret = navi12_get_smu_metrics_data(smu, member, value);

		else

			ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
@@ -928,10 +921,10 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu, 
	default:

		if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		      IP_VERSION(11, 0, 5)) &&

		     smu_version > 0x00351F00) ||

		     smu->smc_fw_version > 0x00351F00) ||

		    ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		      IP_VERSION(11, 0, 0)) &&

		     smu_version > 0x002A3B00))

		     smu->smc_fw_version > 0x002A3B00))

			ret = navi10_get_smu_metrics_data(smu, member, value);

		else

			ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
@@ -2847,19 +2840,12 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 
	struct amdgpu_device *adev = smu->adev;

	uint8_t umc_fw_greater_than_v136 = false;

	uint8_t umc_fw_disable_cdr = false;

	uint32_t pmfw_version;

	uint32_t param;

	int ret = 0;



	if (!navi10_need_umc_cdr_workaround(smu))

		return 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);

	if (ret) {

		dev_err(adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	/*

	 * The messages below are only supported by Navi10 42.53.0 and later

	 * PMFWs and Navi14 53.29.0 and later PMFWs.
@@ -2868,9 +2854,9 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu) 
	 * - PPSMC_MSG_GetUMCFWWA

	 */

	if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&

	     (pmfw_version >= 0x2a3500)) ||

	     (smu->smc_fw_version >= 0x2a3500)) ||

	    ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) &&

	     (pmfw_version >= 0x351D00))) {

	     (smu->smc_fw_version >= 0x351D00))) {

		ret = smu_cmn_send_smc_msg_with_param(smu,

						      SMU_MSG_GET_UMC_FW_WA,

						      0,
@@ -3355,18 +3341,11 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 
				      void **table)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t smu_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(adev->dev, "Failed to get smu version!\n");

		return ret;

	}



	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {

	case IP_VERSION(11, 0, 9):

		if (smu_version > 0x00341C00)

		if (smu->smc_fw_version > 0x00341C00)

			ret = navi12_get_gpu_metrics(smu, table);

		else

			ret = navi12_get_legacy_gpu_metrics(smu, table);
@@ -3376,10 +3355,10 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, 
	default:

		if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		      IP_VERSION(11, 0, 5)) &&

		     smu_version > 0x00351F00) ||

		     smu->smc_fw_version > 0x00351F00) ||

		    ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		      IP_VERSION(11, 0, 0)) &&

		     smu_version > 0x002A3B00))

		     smu->smc_fw_version > 0x002A3B00))

			ret = navi10_get_gpu_metrics(smu, table);

		else

			ret = navi10_get_legacy_gpu_metrics(smu, table);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+8 −35
Original line number Diff line number Diff line
@@ -1279,7 +1279,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 
	uint32_t mark_index = 0;

	uint32_t gen_speed, lane_width;

	uint32_t min_value, max_value;

	uint32_t smu_version;



	smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1388,10 +1387,9 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 
		 * OD GFX Voltage Offset functionality is supported only by 58.41.0

		 * and onwards SMU firmwares.

		 */

		smu_cmn_get_smc_version(smu, NULL, &smu_version);

		if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		     IP_VERSION(11, 0, 7)) &&

		    (smu_version < 0x003a2900))

		    (smu->smc_fw_version < 0x003a2900))

			break;



		size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
@@ -2148,16 +2146,14 @@ static void sienna_cichlid_dump_od_table(struct smu_context *smu, 
					 OverDriveTable_t *od_table)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t smu_version;



	dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,

							  od_table->GfxclkFmax);

	dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,

							od_table->UclkFmax);



	smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&

	      (smu_version < 0x003a2900)))

	      (smu->smc_fw_version < 0x003a2900)))

		dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);

}
@@ -2235,7 +2231,6 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 
	enum SMU_11_0_7_ODSETTING_ID freq_setting;

	uint16_t *freq_ptr;

	int i, ret = 0;

	uint32_t smu_version;



	if (!smu->od_enabled) {

		dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
@@ -2388,10 +2383,9 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, 
		 * OD GFX Voltage Offset functionality is supported only by 58.41.0

		 * and onwards SMU firmwares.

		 */

		smu_cmn_get_smc_version(smu, NULL, &smu_version);

		if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==

		     IP_VERSION(11, 0, 7)) &&

		    (smu_version < 0x003a2900)) {

		    (smu->smc_fw_version < 0x003a2900)) {

			dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "

						"only by 58.41.0 and onwards SMU firmwares!\n");

			return -EOPNOTSUPP;
@@ -2461,14 +2455,12 @@ static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) 
{

	struct amdgpu_device *adev = smu->adev;

	uint32_t val;

	u32 smu_version;



	/**

	 * SRIOV env will not support SMU mode1 reset

	 * PM FW support mode1 reset from 58.26

	 */

	smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))

	if (amdgpu_sriov_vf(adev) || (smu->smc_fw_version < 0x003a1a00))

		return false;



	/**
@@ -4060,14 +4052,9 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, 


static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)

{

	uint32_t if_version = 0xff, smu_version = 0xff;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);

	if (ret)

		return -EOPNOTSUPP;



	if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)

	if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)

		ret = -EOPNOTSUPP;



	return ret;
@@ -4133,17 +4120,13 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) 
static int sienna_cichlid_gpo_control(struct smu_context *smu,

				      bool enablement)

{

	uint32_t smu_version;

	int ret = 0;





	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {

		ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

		if (ret)

			return ret;



		if (enablement) {

			if (smu_version < 0x003a2500) {

			if (smu->smc_fw_version < 0x003a2500) {

				ret = smu_cmn_send_smc_msg_with_param(smu,

								      SMU_MSG_SetGpoFeaturePMask,

								      GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
@@ -4155,7 +4138,7 @@ static int sienna_cichlid_gpo_control(struct smu_context *smu, 
								      NULL);

			}

		} else {

			if (smu_version < 0x003a2500) {

			if (smu->smc_fw_version < 0x003a2500) {

				ret = smu_cmn_send_smc_msg_with_param(smu,

								      SMU_MSG_SetGpoFeaturePMask,

								      0,
@@ -4174,18 +4157,11 @@ static int sienna_cichlid_gpo_control(struct smu_context *smu, 


static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)

{

	uint32_t smu_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret)

		return ret;



	/*

	 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45

	 * onwards PMFWs.

	 */

	if (smu_version < 0x003A2D00)

	if (smu->smc_fw_version < 0x003A2D00)

		return 0;



	return smu_cmn_send_smc_msg_with_param(smu,
@@ -4332,13 +4308,10 @@ static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu) 


static int sienna_cichlid_mode2_reset(struct smu_context *smu)

{

	u32 smu_version;

	int ret = 0, index;

	struct amdgpu_device *adev = smu->adev;

	int timeout = 100;



	smu_cmn_get_smc_version(smu, NULL, &smu_version);



	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,

						SMU_MSG_DriverMode2Reset);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

+9 −39
Original line number Diff line number Diff line
@@ -225,14 +225,6 @@ static int vangogh_tables_init(struct smu_context *smu) 
{

	struct smu_table_context *smu_table = &smu->smu_table;

	struct smu_table *tables = smu_table->tables;

	uint32_t if_version;

	uint32_t smu_version;

	uint32_t ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);

	if (ret) {

		return ret;

	}



	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),

		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
@@ -243,7 +235,7 @@ static int vangogh_tables_init(struct smu_context *smu) 
	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),

		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);



	if (if_version < 0x3) {

	if (smu->smc_fw_if_version < 0x3) {

		SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),

				PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);

		smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
@@ -256,7 +248,7 @@ static int vangogh_tables_init(struct smu_context *smu) 
		goto err0_out;

	smu_table->metrics_time = 0;



	if (smu_version >= 0x043F3E00)

	if (smu->smc_fw_version >= 0x043F3E00)

		smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_3);

	else

		smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
@@ -430,17 +422,9 @@ static int vangogh_common_get_smu_metrics_data(struct smu_context *smu, 
				       MetricsMember_t member,

				       uint32_t *value)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t if_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, NULL);

	if (ret) {

		dev_err(adev->dev, "Failed to get smu if version!\n");

		return ret;

	}



	if (if_version < 0x3)

	if (smu->smc_fw_if_version < 0x3)

		ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);

	else

		ret = vangogh_get_smu_metrics_data(smu, member, value);
@@ -813,17 +797,9 @@ static int vangogh_print_clk_levels(struct smu_context *smu, 
static int vangogh_common_print_clk_levels(struct smu_context *smu,

			enum smu_clk_type clk_type, char *buf)

{

	struct amdgpu_device *adev = smu->adev;

	uint32_t if_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, NULL);

	if (ret) {

		dev_err(adev->dev, "Failed to get smu if version!\n");

		return ret;

	}



	if (if_version < 0x3)

	if (smu->smc_fw_if_version < 0x3)

		ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);

	else

		ret = vangogh_print_clk_levels(smu, clk_type, buf);
@@ -2011,18 +1987,12 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, 
static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,

				      void **table)

{

	uint32_t if_version;

	uint32_t smu_version;

	uint32_t smu_program;

	uint32_t fw_version;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);

	if (ret)

		return ret;



	smu_program = (smu_version >> 24) & 0xff;

	fw_version = smu_version & 0xffffff;

	smu_program = (smu->smc_fw_version >> 24) & 0xff;

	fw_version = smu->smc_fw_version & 0xffffff;

	if (smu_program == 6) {

		if (fw_version >= 0x3F0800)

			ret = vangogh_get_gpu_metrics_v2_4(smu, table);
@@ -2030,13 +2000,13 @@ static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu, 
			ret = vangogh_get_gpu_metrics_v2_3(smu, table);



	} else {

		if (smu_version >= 0x043F3E00) {

			if (if_version < 0x3)

		if (smu->smc_fw_version >= 0x043F3E00) {

			if (smu->smc_fw_if_version < 0x3)

				ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);

			else

				ret = vangogh_get_gpu_metrics_v2_3(smu, table);

		} else {

			if (if_version < 0x3)

			if (smu->smc_fw_if_version < 0x3)

				ret = vangogh_get_legacy_gpu_metrics(smu, table);

			else

				ret = vangogh_get_gpu_metrics(smu, table);

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

+15 −45
Original line number Diff line number Diff line
@@ -467,18 +467,12 @@ static bool aldebaran_is_primary(struct smu_context *smu) 


static int aldebaran_run_board_btc(struct smu_context *smu)

{

	u32 smu_version;

	int ret;



	if (!aldebaran_is_primary(smu))

		return 0;



	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (ret) {

		dev_err(smu->adev->dev, "Failed to get smu version!\n");

		return ret;

	}

	if (smu_version <= 0x00441d00)

	if (smu->smc_fw_version <= 0x00441d00)

		return 0;



	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
@@ -1769,24 +1763,15 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, 
static int aldebaran_check_ecc_table_support(struct smu_context *smu,

		int *ecctable_version)

{

	uint32_t if_version = 0xff, smu_version = 0xff;

	int ret = 0;



	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);

	if (ret) {

		/* return not support if failed get smu_version */

		ret = -EOPNOTSUPP;

	}



	if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)

		ret = -EOPNOTSUPP;

	else if (smu_version >= SUPPORT_ECCTABLE_SMU_VERSION &&

			smu_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)

	if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)

		return -EOPNOTSUPP;

	else if (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_VERSION &&

			smu->smc_fw_version < SUPPORT_ECCTABLE_V2_SMU_VERSION)

		*ecctable_version = 1;

	else

		*ecctable_version = 2;



	return ret;

	return 0;

}



static ssize_t aldebaran_get_ecc_info(struct smu_context *smu,
@@ -1849,7 +1834,7 @@ static ssize_t aldebaran_get_ecc_info(struct smu_context *smu, 


static int aldebaran_mode1_reset(struct smu_context *smu)

{

	u32 smu_version, fatal_err, param;

	u32 fatal_err, param;

	int ret = 0;

	struct amdgpu_device *adev = smu->adev;

	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
@@ -1860,13 +1845,12 @@ static int aldebaran_mode1_reset(struct smu_context *smu) 
	/*

	* PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07

	*/

	smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if (smu_version < 0x00440700) {

	if (smu->smc_fw_version < 0x00440700) {

		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);

	} else {

		/* fatal error triggered by ras, PMFW supports the flag

		   from 68.44.0 */

		if ((smu_version >= 0x00442c00) && ras &&

		if ((smu->smc_fw_version >= 0x00442c00) && ras &&

		    atomic_read(&ras->in_recovery))

			fatal_err = 1;
@@ -1883,18 +1867,15 @@ static int aldebaran_mode1_reset(struct smu_context *smu) 


static int aldebaran_mode2_reset(struct smu_context *smu)

{

	u32 smu_version;

	int ret = 0, index;

	struct amdgpu_device *adev = smu->adev;

	int timeout = 10;



	smu_cmn_get_smc_version(smu, NULL, &smu_version);



	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,

						SMU_MSG_GfxDeviceDriverReset);



	mutex_lock(&smu->message_lock);

	if (smu_version >= 0x00441400) {

	if (smu->smc_fw_version >= 0x00441400) {

		ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);

		/* This is similar to FLR, wait till max FLR timeout */

		msleep(100);
@@ -1921,7 +1902,7 @@ static int aldebaran_mode2_reset(struct smu_context *smu) 


	} else {

		dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",

				smu_version);

				smu->smc_fw_version);

	}



	if (ret == 1)
@@ -1944,13 +1925,11 @@ static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu) 
{

#if 0

	struct amdgpu_device *adev = smu->adev;

	u32 smu_version;

	uint32_t val;

	/**

	 * PM FW version support mode1 reset from 68.07

	 */

	smu_cmn_get_smc_version(smu, NULL, &smu_version);

	if ((smu_version < 0x00440700))

	if ((smu->smc_fw_version < 0x00440700))

		return false;

	/**

	 * mode1 reset relies on PSP, so we should check if
@@ -1995,19 +1974,10 @@ static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu, 


static int aldebaran_check_bad_channel_info_support(struct smu_context *smu)

{

	uint32_t if_version = 0xff, smu_version = 0xff;

	int ret = 0;

	if (smu->smc_fw_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)

		return -EOPNOTSUPP;



	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);

	if (ret) {

		/* return not support if failed get smu_version */

		ret = -EOPNOTSUPP;

	}



	if (smu_version < SUPPORT_BAD_CHANNEL_INFO_MSG_VERSION)

		ret = -EOPNOTSUPP;



	return ret;

	return 0;

}



static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu,