Commit 7119ca35 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/misc'

- Drop unused struct pci_driver.node member (Mathias Krause)

- Fix documentation typos (Attreyee Mukherjee)

- Use a unique test pattern for each BAR in the pci_endpoint_test to make
  it easier to debug address translation issues (Niklas Cassel)

- Fix kernel-doc issues (Bjorn Helgaas)

* pci/misc:
  PCI: Fix kernel-doc issues
  misc: pci_endpoint_test: Use a unique test pattern for each BAR
  docs: PCI: Fix typos
  PCI: Remove unused 'node' member from struct pci_driver
parents 9946bbb3 2db6b72c
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+1 −1
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@@ -61,7 +61,7 @@ Conditions
==========

The use of threaded interrupts is the most likely condition to trigger
this problem today. Threaded interrupts may not be reenabled after the IRQ
this problem today. Threaded interrupts may not be re-enabled after the IRQ
handler wakes. These "one shot" conditions mean that the threaded interrupt
needs to keep the interrupt line masked until the threaded handler has run.
Especially when dealing with high data rate interrupts, the thread needs to
+1 −1
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@@ -236,7 +236,7 @@ including a full 'lspci -v' so we can add the quirks to the kernel.
Disabling MSIs below a bridge
-----------------------------

Some PCI bridges are not able to route MSIs between busses properly.
Some PCI bridges are not able to route MSIs between buses properly.
In this case, MSIs must be disabled on all devices behind the bridge.

Some bridges allow you to enable MSIs by changing some bits in their
+12 −2
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@@ -263,6 +263,15 @@ static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
	return false;
}

static const u32 bar_test_pattern[] = {
	0xA0A0A0A0,
	0xA1A1A1A1,
	0xA2A2A2A2,
	0xA3A3A3A3,
	0xA4A4A4A4,
	0xA5A5A5A5,
};

static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
				  enum pci_barno barno)
{
@@ -280,11 +289,12 @@ static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
		size = 0x4;

	for (j = 0; j < size; j += 4)
		pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
		pci_endpoint_test_bar_writel(test, barno, j,
					     bar_test_pattern[barno]);

	for (j = 0; j < size; j += 4) {
		val = pci_endpoint_test_bar_readl(test, barno, j);
		if (val != 0xA0A0A0A0)
		if (val != bar_test_pattern[barno])
			return false;
	}

+0 −1
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@@ -2707,7 +2707,6 @@ MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);


static struct pci_driver brcmf_pciedrvr = {
	.node = {},
	.name = KBUILD_MODNAME,
	.id_table = brcmf_pcie_devid_table,
	.probe = brcmf_pcie_probe,
+1 −1
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@@ -115,7 +115,7 @@ struct pci_epc_mem {
 * struct pci_epc - represents the PCI EPC device
 * @dev: PCI EPC device
 * @pci_epf: list of endpoint functions present in this EPC device
 * list_lock: Mutex for protecting pci_epf list
 * @list_lock: Mutex for protecting pci_epf list
 * @ops: function pointers for performing endpoint operations
 * @windows: array of address space of the endpoint controller
 * @mem: first window of the endpoint controller, which corresponds to
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