Commit 714dd09f authored by Marek Vasut's avatar Marek Vasut Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r8a779g0: Describe PCIe root ports 



Add nodes which describe the root ports in the PCIe controller DT nodes.
This can be used together with the pwrctrl driver to control clock and
power supply to a PCIe slot.  For example usage, refer to the Sparrow
Hawk board.

Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@mailbox.org>
Link: https://lore.kernel.org/20250607194541.79176-2-marek.vasut+renesas@mailbox.org


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 0c8bf42e

arch/arm64/boot/dts/renesas/r8a779g0.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -798,6 +798,16 @@ pciec0: pcie@e65d0000 { 
					<0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;

			snps,enable-cdm-check;

			status = "disabled";



			/* PCIe bridge, Root Port */

			pciec0_rp: pci@0,0 {

				#address-cells = <3>;

				#size-cells = <2>;

				reg = <0x0 0x0 0x0 0x0 0x0>;

				compatible = "pciclass,0604";

				device_type = "pci";

				ranges;

			};

		};



		pciec1: pcie@e65d8000 {
@@ -835,6 +845,16 @@ pciec1: pcie@e65d8000 { 
					<0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;

			snps,enable-cdm-check;

			status = "disabled";



			/* PCIe bridge, Root Port */

			pciec1_rp: pci@0,0 {

				#address-cells = <3>;

				#size-cells = <2>;

				reg = <0x0 0x0 0x0 0x0 0x0>;

				compatible = "pciclass,0604";

				device_type = "pci";

				ranges;

			};

		};



		pciec0_ep: pcie-ep@e65d0000 {