Commit 7156c650 authored by John Crispin's avatar John Crispin Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 



The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: default avatarJohn Crispin <john@phrozen.org>
Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 97eb2ac5

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

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Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties: 
      - qcom,ipq5018-cmn-pll

      - qcom,ipq5424-cmn-pll

      - qcom,ipq6018-cmn-pll

      - qcom,ipq8074-cmn-pll

      - qcom,ipq9574-cmn-pll



  reg:

include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h

0 → 100644
+15 −0
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H

#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H



/* CMN PLL core clock. */

#define IPQ8074_CMN_PLL_CLK			0



/* The output clocks from CMN PLL of IPQ8074. */

#define IPQ8074_BIAS_PLL_CC_CLK			1

#define IPQ8074_BIAS_PLL_NSS_NOC_CLK		2

#endif