Commit 71733b8d authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Nirmoy Das
Browse files

drm/xe/xe2: Make subsequent L2 flush sequential 



Issuing the flush on top of an ongoing flush is not desirable.
Lets use lock to make it sequential.

Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240710052750.3031586-1-tejas.upadhyay@intel.com


Signed-off-by: default avatarNirmoy Das <nirmoy.das@intel.com>
parent 33891539

drivers/gpu/drm/xe/xe_device.c

+2 −0
Original line number Diff line number Diff line
@@ -833,10 +833,12 @@ void xe_device_l2_flush(struct xe_device *xe) 
	if (err)

		return;



	spin_lock(&gt->global_invl_lock);

	xe_mmio_write32(gt, XE2_GLOBAL_INVAL, 0x1);



	if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))

		xe_gt_err_once(gt, "Global invalidation timeout\n");

	spin_unlock(&gt->global_invl_lock);



	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);

}

drivers/gpu/drm/xe/xe_gt.c

+1 −0
Original line number Diff line number Diff line
@@ -387,6 +387,7 @@ int xe_gt_init_early(struct xe_gt *gt) 


	xe_force_wake_init_gt(gt, gt_to_fw(gt));

	xe_pcode_init(gt);

	spin_lock_init(&gt->global_invl_lock);



	return 0;

}

drivers/gpu/drm/xe/xe_gt_types.h

+6 −0
Original line number Diff line number Diff line
@@ -362,6 +362,12 @@ struct xe_gt { 
	 */

	spinlock_t mcr_lock;



	/**

	 * @global_invl_lock: protects the register for the duration

	 *    of a global invalidation of l2 cache

	 */

	spinlock_t global_invl_lock;



	/** @wa_active: keep track of active workarounds */

	struct {

		/** @wa_active.gt: bitmap with active GT workarounds */