Commit 7187ea09 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-03-01' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Bunch of fixes, xe, amdgpu, nouveau and tegra all have a few. Then
  drm/bridge including some drivers/soc fallout fixes. The biggest thing
  in here is a new unit test for some buddy allocator fixes, otherwise a
  misc fbcon, ttm unit test and one msm revert.

  Seems pretty normal for this stage.

  buddy:
   - two allocation fixes + unit test

  fbcon:
   - font restore syzkaller fix

  ttm:
   - kunit test fix

  bridge:
   - fix aux-hpd leaks
   - fix aux-hpd registration
   - fix use after free in soc/qcom
   - fix boot on soc/qcom

  xe:
   - A couple of tracepoint updates from Priyanka and Lucas
   - Make sure BINDs are completed before accepting UNBINDs on LR vms
   - Don't arbitrarily restrict max number of batched binds
   - Add uapi for dumpable bos (agreed on IRC)
   - Remove unused uapi flags and a leftover comment
   - A couple of fixes related to the execlist backend

  msm:
   - DP: Revert a change which was causing a HDP regression

  amdgpu:
   - Fix potential buffer overflow
   - Fix power min cap
   - Suspend/resume fix
   - SI PM fix
   - eDP fix

  nouveau:
   - fix a misreported VRAM sizing
   - fix a regression in suspend/resume due to freeing

  tegra:
   - host1x reset fix
   - only remove existing driver if display is possible"

* tag 'drm-fixes-2024-03-01' of https://gitlab.freedesktop.org/drm/kernel: (32 commits)
  drm/nouveau: keep DMA buffers required for suspend/resume
  nouveau: report byte usage in VRAM usage
  drm/xe/xe_trace: Add move_lacks_source detail to xe_bo_move trace
  drm/xe: Deny unbinds if uapi ufence pending
  drm/xe: Expose user fence from xe_sync_entry
  drm/xe: Use pointers in trace events
  drm/xe/xe_bo_move: Enhance xe_bo_move trace
  drm/xe/mmio: fix build warning for BAR resize on 32-bit
  drm/xe: get rid of MAX_BINDS
  drm/xe: Use vmalloc for array of bind allocation in bind IOCTL
  drm/xe: Don't support execlists in xe_gt_tlb_invalidation layer
  drm/xe: Fix execlist splat
  drm/xe/uapi: Remove unused flags
  drm/xe/uapi: Remove DRM_XE_VM_BIND_FLAG_ASYNC comment left over
  drm/xe: Add uapi for dumpable bos
  drm/amd/display: Add monitor patch for specific eDP
  Revert "drm/msm/dp: use drm_bridge_hpd_notify() to report HPD status changes"
  drm/tests/drm_buddy: add alloc_range_bias test
  drm/buddy: check range allocation matches alignment
  drm/buddy: fix range bias
  ...
parents 161671a6 f6ecfdad

drivers/gpu/drm/Kconfig

+3 −2
Original line number Diff line number Diff line
@@ -199,7 +199,7 @@ config DRM_TTM 
config DRM_TTM_KUNIT_TEST

        tristate "KUnit tests for TTM" if !KUNIT_ALL_TESTS

        default n

        depends on DRM && KUNIT && MMU

        depends on DRM && KUNIT && MMU && (UML || COMPILE_TEST)

        select DRM_TTM

        select DRM_EXPORT_FOR_TESTS if m

        select DRM_KUNIT_TEST_HELPERS
@@ -207,7 +207,8 @@ config DRM_TTM_KUNIT_TEST 
        help

          Enables unit tests for TTM, a GPU memory manager subsystem used

          to manage memory buffers. This option is mostly useful for kernel

          developers.

          developers. It depends on (UML || COMPILE_TEST) since no other driver

          which uses TTM can be loaded while running the tests.



          If in doubt, say "N".

drivers/gpu/drm/amd/amdgpu/soc15.c

+25 −20
Original line number Diff line number Diff line
@@ -574,11 +574,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev) 
		return AMD_RESET_METHOD_MODE1;

}



static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)

{

	u32 sol_reg;



	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);



	/* Will reset for the following suspend abort cases.

	 * 1) Only reset limit on APU side, dGPU hasn't checked yet.

	 * 2) S3 suspend abort and TOS already launched.

	 */

	if (adev->flags & AMD_IS_APU && adev->in_s3 &&

			!adev->suspend_complete &&

			sol_reg)

		return true;



	return false;

}



static int soc15_asic_reset(struct amdgpu_device *adev)

{

	/* original raven doesn't have full asic reset */

	if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||

	    (adev->apu_flags & AMD_APU_IS_RAVEN2))

	/* On the latest Raven, the GPU reset can be performed

	 * successfully. So now, temporarily enable it for the

	 * S3 suspend abort case.

	 */

	if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||

	    (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&

		!soc15_need_reset_on_resume(adev))

		return 0;



	switch (soc15_asic_reset_method(adev)) {
@@ -1298,24 +1321,6 @@ static int soc15_common_suspend(void *handle) 
	return soc15_common_hw_fini(adev);

}



static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)

{

	u32 sol_reg;



	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);



	/* Will reset for the following suspend abort cases.

	 * 1) Only reset limit on APU side, dGPU hasn't checked yet.

	 * 2) S3 suspend abort and TOS already launched.

	 */

	if (adev->flags & AMD_IS_APU && adev->in_s3 &&

			!adev->suspend_complete &&

			sol_reg)

		return true;



	return false;

}



static int soc15_common_resume(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+4 −2
Original line number Diff line number Diff line
@@ -67,6 +67,8 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) 
	/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */

	case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):

	case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):

	case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):

	case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):

		DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);

		edid_caps->panel_patch.remove_sink_ext_caps = true;

		break;
@@ -120,6 +122,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps( 


	edid_caps->edid_hdmi = connector->display_info.is_hdmi;



	apply_edid_quirks(edid_buf, edid_caps);



	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);

	if (sad_count <= 0)

		return result;
@@ -146,8 +150,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps( 
	else

		edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;



	apply_edid_quirks(edid_buf, edid_caps);



	kfree(sads);

	kfree(sadb);

drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

+5 −0
Original line number Diff line number Diff line
@@ -76,6 +76,11 @@ static void map_hw_resources(struct dml2_context *dml2, 
			in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;

		}

		for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) {

			if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) {

				dml_print("DML::%s: Index out of bounds: i=%d, __DML2_WRAPPER_MAX_STREAMS_PLANES__=%d\n",

					  __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__);

				break;

			}

			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];

			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;

			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

+29 −0
Original line number Diff line number Diff line
@@ -6925,6 +6925,23 @@ static int si_dpm_enable(struct amdgpu_device *adev) 
	return 0;

}



static int si_set_temperature_range(struct amdgpu_device *adev)

{

	int ret;



	ret = si_thermal_enable_alert(adev, false);

	if (ret)

		return ret;

	ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);

	if (ret)

		return ret;

	ret = si_thermal_enable_alert(adev, true);

	if (ret)

		return ret;



	return ret;

}



static void si_dpm_disable(struct amdgpu_device *adev)

{

	struct rv7xx_power_info *pi = rv770_get_pi(adev);
@@ -7608,6 +7625,18 @@ static int si_dpm_process_interrupt(struct amdgpu_device *adev, 


static int si_dpm_late_init(void *handle)

{

	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (!adev->pm.dpm_enabled)

		return 0;



	ret = si_set_temperature_range(adev);

	if (ret)

		return ret;

#if 0 //TODO ?

	si_dpm_powergate_uvd(adev, true);

#endif

	return 0;

}