Commit 719da04f authored by Hojin Nam's avatar Hojin Nam Committed by Will Deacon
Browse files

perf: CXL: fix mismatched cpmu event opcode 



S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
r3.0 3.3.9 Table 3.43. However, it is defined as 3 in macro definition.

Fixes: 5d7107c7 ("perf: CXL Performance Monitoring Unit driver")
Signed-off-by: default avatarHojin Nam <hj96.nam@samsung.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20240208013415epcms2p2904187c8a863f4d0d2adc980fb91a2dc@epcms2p2


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 61da7c8e

drivers/perf/cxl_pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -419,7 +419,7 @@ static struct attribute *cxl_pmu_event_attrs[] = { 
	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp,			CXL_PMU_GID_S2M_NDR, BIT(0)),

	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps,			CXL_PMU_GID_S2M_NDR, BIT(1)),

	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe,			CXL_PMU_GID_S2M_NDR, BIT(2)),

	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,		CXL_PMU_GID_S2M_NDR, BIT(3)),

	CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,		CXL_PMU_GID_S2M_NDR, BIT(4)),

	/* CXL rev 3.0 Table 3-46 S2M DRS opcodes */

	CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata,			CXL_PMU_GID_S2M_DRS, BIT(0)),

	CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm,		CXL_PMU_GID_S2M_DRS, BIT(1)),